[Socbuilder-discussion] SoC Builder status

[John E. <joh...@hp...>]

Hello,  anyone out there????

SoC Builder seems to have had a quick "flash_in_the_pan" start and zero 
follow through.

There is still a need for this type of tool and I would like to rekindle 
this project. Is
anybody else interested?

Lets start off with a discussion on design reuse and explore the design 
challenges and
how  teams are currently building chips with ip cores.  We need to do 
our homework
before even thinking about  starting to build a tool.

I see the first  step as creating a  design guideline manual for IP 
developers. This would
detail all the Design_for_Synthesis, Design_for_Test and  
Design_for_Reuse requirements.
It would serve as an interface spec to tell the developers what to 
create and tell the chip
system builders what to expect.

I would include sections on clock and reset design methods to show what 
you can and cannot do.

We also need to work out a method for the developers to pass their IP 
needs to the chip
builders. Developers need IP like pads, srams, clocks, resets, address 
space etc. We need
to define a set of "system calls"  for these functions rather than 
having to customize every
piece of IP for each chip.

The best book that I have found on reuse is "Reuse Methodology Manual" 
By Michael
Keating. Anybody know of any others? Are there any industry groups 
working on a usable
design reuse standard?

john_eaton  at users.sourceforge.net