https://sourceforge.net/p/smgenerator/wiki/Home/Recent changes to HomeenThu, 10 Mar 2016 02:51:27 -0000https://sourceforge.net/p/smgenerator/wiki/Home/<div class="markdown_content"><pre>--- v1 +++ v2 @@ -1,8 +1,4 @@ -Welcome to your wiki! - -This is the default page, edit it as you see fit. To add a new page simply reference it within brackets, e.g.: [SamplePage]. - -The wiki uses [Markdown](/p/smgenerator/wiki/markdown_syntax/) syntax. - +SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing +[[project_screenshots]] [[project_admins]] [[download_button]] </pre> </div> estoolThu, 10 Mar 2016 02:51:27 -0000https://sourceforge.neta071ef255afa216951454e43a0312fa10933fec7https://sourceforge.net/p/smgenerator/wiki/Home/<div class="markdown_content"><p>Welcome to your wiki!</p> <p>This is the default page, edit it as you see fit. To add a new page simply reference it within brackets, e.g.: <span>[SamplePage]</span>.</p> <p>The wiki uses <a class="" href="/p/smgenerator/wiki/markdown_syntax/">Markdown</a> syntax.</p> <p></p><p><a href="/u/estool/"> estool</a><br /></p><br /> <p><span class="download-button-5166df2ae88f3d0ab9718da9" style="margin-bottom: 1em; display: block;"></span></p></div> estoolThu, 11 Apr 2013 16:04:59 -0000https://sourceforge.net0df64081d690b29708e3cebfe8743df4299d803c