simit-arm-cvs Mailing List for SimIt-ARM
Brought to you by:
weiqin04
Menu
▾
▴
simit-arm-cvs
You can subscribe to this list here.
| 2004 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
(9) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2005 |
Jan
|
Feb
(26) |
Mar
(47) |
Apr
(9) |
May
(6) |
Jun
|
Jul
|
Aug
(7) |
Sep
(6) |
Oct
|
Nov
|
Dec
|
| 2006 |
Jan
|
Feb
|
Mar
|
Apr
(3) |
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
|
From: Wei Q. <wei...@us...> - 2006-04-08 04:59:06
|
Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv15297 Modified Files: Tag: sc_branch BIU.h main.cpp more_managers.cpp Log Message: some miscelaneous changes Index: more_managers.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/more_managers.cpp,v retrieving revision 1.2.2.9 retrieving revision 1.2.2.10 diff -C2 -d -r1.2.2.9 -r1.2.2.10 *** more_managers.cpp 20 Mar 2005 16:03:24 -0000 1.2.2.9 --- more_managers.cpp 8 Apr 2006 04:59:00 -0000 1.2.2.10 *************** *** 4,7 **** --- 4,8 ---- //#include "emu_device.hpp" #include "nwfpe.h" + #include <csignal> using namespace simulator; *************** *** 281,285 **** "for instruction 0x%08x : " " more than 16 memory references.\n", iw); ! exit(1); break; case arm_simulator::CP_FLAG_EARLY_DONE: --- 282,286 ---- "for instruction 0x%08x : " " more than 16 memory references.\n", iw); ! raise(SIGINT); break; case arm_simulator::CP_FLAG_EARLY_DONE: *************** *** 287,291 **** "for instruction 0x%08x : " "done signal earlier than expected.\n", iw); ! exit(1); break; case arm_simulator::CP_FLAG_TIME_OUT: --- 288,292 ---- "for instruction 0x%08x : " "done signal earlier than expected.\n", iw); ! raise(SIGINT); break; case arm_simulator::CP_FLAG_TIME_OUT: *************** *** 293,297 **** "for instruction 0x%08x : " "time out.\n", iw); ! exit(1); break; } --- 294,298 ---- "for instruction 0x%08x : " "time out.\n", iw); ! raise(SIGINT); break; } Index: main.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/main.cpp,v retrieving revision 1.2.2.10 retrieving revision 1.2.2.11 diff -C2 -d -r1.2.2.10 -r1.2.2.11 *** main.cpp 27 Mar 2005 05:33:33 -0000 1.2.2.10 --- main.cpp 8 Apr 2006 04:59:00 -0000 1.2.2.11 *************** *** 71,75 **** } } ! /* emulator instance */ if(prog_name) --- 71,75 ---- } } ! /* emulator instance */ if(prog_name) Index: BIU.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/Attic/BIU.h,v retrieving revision 1.2.2.3 retrieving revision 1.2.2.4 diff -C2 -d -r1.2.2.3 -r1.2.2.4 *** BIU.h 20 Feb 2005 08:14:22 -0000 1.2.2.3 --- BIU.h 8 Apr 2006 04:59:00 -0000 1.2.2.4 *************** *** 52,59 **** // if acknowledge received, then turn off busy ! if (busy && inAck) { ! acked = true; ! busy = false; ! } // statistics counting --- 52,58 ---- // if acknowledge received, then turn off busy ! if (acked) busy = false; ! ! acked = inAck; // statistics counting |
|
From: Wei Q. <wei...@us...> - 2006-04-08 04:48:52
|
Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv8301 Modified Files: Tag: sc_branch armsim.cpp Log Message: renamed some cache functions Index: armsim.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.cpp,v retrieving revision 1.2.2.12 retrieving revision 1.2.2.13 diff -C2 -d -r1.2.2.12 -r1.2.2.13 *** armsim.cpp 27 Mar 2005 05:43:00 -0000 1.2.2.12 --- armsim.cpp 8 Apr 2006 04:48:48 -0000 1.2.2.13 *************** *** 258,266 **** mSC->update_on_clock(); ! itlb->updateOnClockTick(); ! dtlb->updateOnClockTick(); ! icache->updateOnClockTick(); ! dcache->updateOnClockTick(); mmu_update(); --- 258,266 ---- mSC->update_on_clock(); ! itlb->update_on_clock(); ! dtlb->update_on_clock(); ! icache->update_on_clock(); ! dcache->update_on_clock(); mmu_update(); |
|
From: Wei Q. <wei...@us...> - 2006-04-08 04:46:47
|
Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv6970 Modified Files: Tag: sc_branch cache.h Log Message: renamed some functions in cache, fixed a compiler problem Index: cache.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/cache.h,v retrieving revision 1.3.2.7 retrieving revision 1.3.2.8 diff -C2 -d -r1.3.2.7 -r1.3.2.8 *** cache.h 20 Mar 2005 16:03:24 -0000 1.3.2.7 --- cache.h 8 Apr 2006 04:46:43 -0000 1.3.2.8 *************** *** 19,31 **** }; ! uint32_t index(uint32_t addr) { return (addr/bsize)%(n_block/n_assoc); } ! uint32_t tag(uint32_t addr) { return (addr/(bsize*n_block/n_assoc)); } ! uint32_t reconstruct_address(uint32_t index, uint32_t tag) { return (tag*(n_block/n_assoc) + index)*bsize; } --- 19,31 ---- }; ! uint32_t get_index(uint32_t addr) { return (addr/bsize)%(n_block/n_assoc); } ! uint32_t get_tag(uint32_t addr) { return (addr/(bsize*n_block/n_assoc)); } ! uint32_t get_address(uint32_t index, uint32_t tag) { return (tag*(n_block/n_assoc) + index)*bsize; } *************** *** 41,46 **** /* check if the address is in cache */ ! struct block_t *lookup(uint32_t addr) { ! uint32_t ind = index(addr), atag = tag(addr); for (uint32_t i=0; i<n_assoc; i++) if (tags[ind][i].tag == atag && tags[ind][i].valid) --- 41,46 ---- /* check if the address is in cache */ ! struct block_t *look_up(uint32_t addr) { ! uint32_t ind = get_index(addr), atag = get_tag(addr); for (uint32_t i=0; i<n_assoc; i++) if (tags[ind][i].tag == atag && tags[ind][i].valid) *************** *** 50,56 **** /* allocate a cache block, return true if eviction happened */ ! struct block_t *allocateBlock(uint32_t addr) { ! uint32_t ind = index(addr); struct block_t *theblock = &tags[ind][choose_round_robin(ind)]; --- 50,56 ---- /* allocate a cache block, return true if eviction happened */ ! struct block_t *allocate_block(uint32_t addr) { ! uint32_t ind = get_index(addr); struct block_t *theblock = &tags[ind][choose_round_robin(ind)]; *************** *** 71,79 **** cache(const std::string& name) : name(name) {} ~cache() {} /* invalidate a line of cache */ bool invalidate(uint32_t addr) { ! struct block_t *blk = lookup(addr); if (!blk || !blk->valid) return false; blk->valid = false; --- 71,80 ---- cache(const std::string& name) : name(name) {} + ~cache() {} /* invalidate a line of cache */ bool invalidate(uint32_t addr) { ! struct block_t *blk = look_up(addr); if (!blk || !blk->valid) return false; blk->valid = false; *************** *** 108,115 **** void reset() { ! memset(tags, 0, sizeof(tags)); ! memset(round_robin_index, 0, sizeof(round_robin_index)); ! read_busy = false; ! latency = 0; nReads = 0; nReadMisses = 0; --- 109,116 ---- void reset() { ! memset(cache<n_block,n_assoc,bsize>::tags, 0, sizeof(cache<n_block,n_assoc,bsize>::tags)); ! memset(cache<n_block,n_assoc,bsize>::round_robin_index, 0, ! sizeof(cache<n_block,n_assoc,bsize>::round_robin_index)); ! delay = 0; nReads = 0; nReadMisses = 0; *************** *** 118,132 **** bool read(uint32_t addr, uint32_t size) { ! if (read_busy) return false; ! tag_t *ablock = lookup(addr); if (!ablock) { nReadMisses++; - read_busy = true; /* read the block in */ ! latency = r_latency; ! reqTag = allocateBlock(addr); ! reqTag->tag = tag(addr); reqTag->valid = true; --- 119,133 ---- bool read(uint32_t addr, uint32_t size) { ! if (delay) return false; ! tag_t *ablock = look_up(addr); if (!ablock) { + nReadMisses++; /* read the block in */ ! delay = r_latency; ! reqTag = allocate_block(addr); ! reqTag->tag = get_tag(addr); reqTag->valid = true; *************** *** 138,156 **** } ! void updateOnClockTick() { ! if (read_busy) { ! if (latency==0) ! read_busy = false; ! else latency--; ! } } void PrintStats(FILE *fp) { ! fprintf(fp, "Total %s reads: ", name.c_str()); dump_int64(nReads, fp); ! fprintf(fp, "\nTotal %s read misses: ", name.c_str()); dump_int64(nReadMisses, fp); ! fprintf(fp, "\n%s hit ratio: %.3f%%\n", name.c_str(), 100.0*(nReads-nReadMisses)/(nReads)); } --- 139,153 ---- } ! void update_on_clock() { ! if (delay) delay--; } void PrintStats(FILE *fp) { ! fprintf(fp, "Total %s reads: ", cache<n_block,n_assoc,bsize>::name.c_str()); dump_int64(nReads, fp); ! fprintf(fp, "\nTotal %s read misses: ", cache<n_block,n_assoc,bsize>::name.c_str()); dump_int64(nReadMisses, fp); ! fprintf(fp, "\n%s hit ratio: %.3f%%\n", cache<n_block,n_assoc,bsize>::name.c_str(), 100.0*(nReads-nReadMisses)/(nReads)); } *************** *** 158,163 **** protected: tag_t *reqTag; ! bool read_busy; ! uint32_t latency; uint64_t nReads, nReadMisses; --- 155,159 ---- protected: tag_t *reqTag; ! uint32_t delay; uint64_t nReads, nReadMisses; *************** *** 184,192 **** void reset() { ! memset(tags, 0, sizeof(tags)); memset(values, 0, sizeof(values)); ! memset(round_robin_index, 0, sizeof(round_robin_index)); update_state = NO_UPDATE; - delay_flag = false; nReads = 0; nReadMisses = 0; --- 180,188 ---- void reset() { ! memset(cache<n_block,n_assoc,bsize>::tags, 0, sizeof(cache<n_block,n_assoc,bsize>::tags)); memset(values, 0, sizeof(values)); ! memset(cache<n_block,n_assoc,bsize>::round_robin_index, 0, ! sizeof(cache<n_block,n_assoc,bsize>::round_robin_index)); update_state = NO_UPDATE; nReads = 0; nReadMisses = 0; *************** *** 200,208 **** /* check that this is not accross cache line boundary */ if (addr/bsize!=(addr+size-1)/bsize) { ! fprintf(stderr, "rcache fault: addr=%08x size=%d\n", addr, size); exit(1); } ! reqTag = lookup(addr); if (!reqTag) { --- 196,206 ---- /* check that this is not accross cache line boundary */ if (addr/bsize!=(addr+size-1)/bsize) { ! fprintf(stderr, "%s: illegal access crosses line boundary - " ! "addr=%08x size=%d\n", cache<n_block,n_assoc,bsize>::name.c_str(), ! addr, size); exit(1); } ! reqTag = look_up(addr); if (!reqTag) { *************** *** 210,227 **** /* read the blocks in */ ! reqTag = allocateBlock(addr); ! reqTag->tag = tag(addr); reqTag->valid = true; ! reqLine = &values[0][0] + (reqTag - &tags[0][0]); ! waddr = addr/bsize*bsize; ! // if the channel is busy, wait */ if (biu.is_busy()) { update_state = PENDING_LOAD; } else { ! biu.post_request(true, waddr, bsize, reqLine->data); ! delay_flag = true; update_state = WAITING_LOAD; } --- 208,225 ---- /* read the blocks in */ ! reqTag = allocate_block(addr); ! reqTag->tag = get_tag(addr); reqTag->valid = true; ! reqLine = &values[0][0] + (reqTag - &cache<n_block,n_assoc,bsize>::tags[0][0]); ! /* align the address at line boundary */ ! aligned_addr = addr/bsize*bsize; ! /* if the channel is busy, wait */ if (biu.is_busy()) { update_state = PENDING_LOAD; } else { ! biu.post_request(true, aligned_addr, bsize, reqLine->data); update_state = WAITING_LOAD; } *************** *** 230,250 **** } ! reqLine = &values[0][0] + (reqTag - &tags[0][0]); uint8_t *ptr = reqLine->data + addr%bsize; ! if (size==1) *val = (uint32_t)(*ptr); else if (size==2) #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! *val = swap_half_word(* reinterpret_cast<uint16_t *>(ptr)); #else *val = *reinterpret_cast<uint16_t *>(ptr); #endif else { ! #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! *val = swap_word(* reinterpret_cast<uint32_t *>(ptr)); ! #else ! *val = *reinterpret_cast<uint32_t *>(ptr); ! #endif } --- 228,253 ---- } ! reqLine = &values[0][0] + (reqTag - &cache<n_block,n_assoc,bsize>::tags[0][0]); uint8_t *ptr = reqLine->data + addr%bsize; ! if (size==4) ! #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! *val = swap_word(*reinterpret_cast<uint32_t *>(ptr)); ! #else ! *val = *reinterpret_cast<uint32_t *>(ptr); ! #endif ! else if (size==1) *val = (uint32_t)(*ptr); else if (size==2) #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! *val = swap_half_word(*reinterpret_cast<uint16_t *>(ptr)); #else *val = *reinterpret_cast<uint16_t *>(ptr); #endif else { ! fprintf(stderr, "%s: illegal access size, must be 1, 2 or 4 - " ! "addr=%08x size=%d\n", cache<n_block,n_assoc,bsize>::name.c_str(), ! addr, size); ! exit(1); } *************** *** 253,285 **** } ! void updateOnClockTick() { ! ! if (delay_flag) { ! delay_flag = false; ! return; ! } ! ! if (update_state!=NO_UPDATE && biu.get_ack()) { ! if (update_state==PENDING_LOAD) { ! if (!biu.is_busy()) { ! biu.post_request(true, waddr, bsize, reqLine->data); ! delay_flag = true; ! update_state = WAITING_LOAD; ! } ! } ! else { ! update_state = NO_UPDATE; } } } void PrintStats(FILE *fp) { ! fprintf(fp, "Total %s reads: ", name.c_str()); dump_int64(nReads, fp); ! fprintf(fp, "\nTotal %s read misses: ", name.c_str()); dump_int64(nReadMisses, fp); ! fprintf(fp, "\n%s hit ratio: %.3f%%\n", name.c_str(), 100.0*(nReads-nReadMisses)/(nReads)); } --- 256,279 ---- } ! void update_on_clock() { ! if (update_state==PENDING_LOAD) { ! if (!biu.is_busy()) { ! biu.post_request(true, aligned_addr, bsize, reqLine->data); ! update_state = WAITING_LOAD; } } + else if (update_state==WAITING_LOAD && biu.get_ack()) { + update_state = NO_UPDATE; + } } void PrintStats(FILE *fp) { ! fprintf(fp, "Total %s reads: ", cache<n_block,n_assoc,bsize>::name.c_str()); dump_int64(nReads, fp); ! fprintf(fp, "\nTotal %s read misses: ", cache<n_block,n_assoc,bsize>::name.c_str()); dump_int64(nReadMisses, fp); ! fprintf(fp, "\n%s hit ratio: %.3f%%\n", cache<n_block,n_assoc,bsize>::name.c_str(), 100.0*(nReads-nReadMisses)/(nReads)); } *************** *** 295,307 **** } update_state; ! uint32_t waddr; uint64_t nReads, nReadMisses; - bool delay_flag; - tag_t *reqTag; struct data_t *reqLine; struct data_t values[n_block/n_assoc][n_assoc]; - }; --- 289,298 ---- } update_state; ! uint32_t aligned_addr; uint64_t nReads, nReadMisses; tag_t *reqTag; struct data_t *reqLine; struct data_t values[n_block/n_assoc][n_assoc]; }; *************** *** 332,341 **** void reset() { ! memset(tags, 0, sizeof(tags)); memset(values, 0, sizeof(values)); ! memset(round_robin_index, 0, sizeof(round_robin_index)); update_state = NO_UPDATE; - delay_flag = false; flush_only = false; --- 323,332 ---- void reset() { ! memset(cache<n_block,n_assoc,bsize>::tags, 0, sizeof(cache<n_block,n_assoc,bsize>::tags)); memset(values, 0, sizeof(values)); ! memset(cache<n_block,n_assoc,bsize>::round_robin_index, 0, ! sizeof(cache<n_block,n_assoc,bsize>::round_robin_index)); update_state = NO_UPDATE; flush_only = false; *************** *** 352,360 **** /* check that this is not across cache line boundary */ if (addr/bsize!=(addr+size-1)/bsize) { ! fprintf(stderr, "rwcache fault: addr=%08x size=%d\n", addr, size); exit(1); } ! reqTag = lookup(addr); if (!reqTag) { --- 343,353 ---- /* check that this is not across cache line boundary */ if (addr/bsize!=(addr+size-1)/bsize) { ! fprintf(stderr, "%s: illegal access crosses line boundary - " ! "addr=%08x size=%d\n", cache<n_block,n_assoc,bsize>::name.c_str(), ! addr, size); exit(1); } ! reqTag = look_up(addr); if (!reqTag) { *************** *** 363,370 **** /* read the block in */ ! reqTag = allocateBlock(addr); ! reqLine = &values[0][0] + (reqTag - &tags[0][0]); ! waddr = addr/bsize*bsize; // need to flush this line --- 356,363 ---- /* read the block in */ ! reqTag = allocate_block(addr); ! reqLine = &values[0][0] + (reqTag - &cache<n_block,n_assoc,bsize>::tags[0][0]); ! aligned_addr = addr/bsize*bsize; // need to flush this line *************** *** 372,377 **** // get the address of the line ! uint32_t flush_index = (reqTag-&tags[0][0])/n_assoc; ! faddr = reconstruct_address(flush_index, reqTag->tag); flush_only = false; --- 365,370 ---- // get the address of the line ! uint32_t flush_index = (reqTag-&cache<n_block,n_assoc,bsize>::tags[0][0])/n_assoc; ! flush_addr = get_address(flush_index, reqTag->tag); flush_only = false; *************** *** 381,386 **** } else { ! biu.post_request(false, faddr, bsize, reqLine->data); ! delay_flag = true; update_state = WAITING_FLUSH; } --- 374,378 ---- } else { ! biu.post_request(false, flush_addr, bsize, reqLine->data); update_state = WAITING_FLUSH; } *************** *** 393,403 **** } else { ! biu.post_request(true, waddr, bsize, reqLine->data); ! delay_flag = true; update_state = WAITING_LOAD; } } ! reqTag->tag = tag(addr); reqTag->valid = true; --- 385,394 ---- } else { ! biu.post_request(true, aligned_addr, bsize, reqLine->data); update_state = WAITING_LOAD; } } ! reqTag->tag = get_tag(addr); reqTag->valid = true; *************** *** 405,425 **** } ! reqLine = &values[0][0] + (reqTag - &tags[0][0]); uint8_t *ptr = reqLine->data + addr%bsize; ! if (size==1) ! *val = (uint32_t)(*ptr); ! else if (size==2) #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! *val = swap_half_word(* reinterpret_cast<uint16_t *>(ptr)); #else ! *val = *reinterpret_cast<uint16_t *>(ptr); #endif ! else #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! *val = swap_word(* reinterpret_cast<uint32_t *>(ptr)); #else ! *val = *reinterpret_cast<uint32_t *>(ptr); #endif nReads++; return true; --- 396,423 ---- } ! reqLine = &values[0][0] + (reqTag - &cache<n_block,n_assoc,bsize>::tags[0][0]); uint8_t *ptr = reqLine->data + addr%bsize; ! if (size==4) #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! *val = swap_word(*reinterpret_cast<uint32_t *>(ptr)); #else ! *val = *reinterpret_cast<uint32_t *>(ptr); #endif ! else if (size==1) ! *val = (uint32_t)(*ptr); ! else if (size==2) #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! *val = swap_half_word(*reinterpret_cast<uint16_t *>(ptr)); #else ! *val = *reinterpret_cast<uint16_t *>(ptr); #endif + else { + fprintf(stderr, "%s: illegal access size, must be 1, 2 or 4 - " + "addr=%08x size=%d\n", cache<n_block,n_assoc,bsize>::name.c_str(), + addr, size); + exit(1); + } + nReads++; return true; *************** *** 433,445 **** /* check that this is not across cache line boundary */ if (addr/bsize!=(addr+size-1)/bsize) { ! fprintf(stderr, "rwcache fault: addr=%08x size=%d\n", addr, size); exit(1); } /* if in cache, then update the cache line with data */ ! reqTag = lookup(addr); if (reqTag) { ! reqLine = &values[0][0] + (reqTag - &tags[0][0]); reqLine->dirty = true; // dirty line now --- 431,445 ---- /* check that this is not across cache line boundary */ if (addr/bsize!=(addr+size-1)/bsize) { ! fprintf(stderr, "%s: illegal access crosses line boundary - " ! "addr=%08x size=%d\n", cache<n_block,n_assoc,bsize>::name.c_str(), ! addr, size); exit(1); } /* if in cache, then update the cache line with data */ ! reqTag = look_up(addr); if (reqTag) { ! reqLine = &values[0][0] + (reqTag - &cache<n_block,n_assoc,bsize>::tags[0][0]); reqLine->dirty = true; // dirty line now *************** *** 448,464 **** /* swap the value if necessary */ #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! if (size==4) wval = swap_half_word((uint16_t)val); ! else if (size==2) wval = swap_word(val); ! else wval = val; #else ! wval = val; #endif ! if (size==1) ! *ptr = (uint8_t)wval; else if (size==2) ! *reinterpret_cast<uint16_t *>(ptr) = wval; ! else ! *reinterpret_cast<uint32_t *>(ptr) = wval; nWrites++; --- 448,469 ---- /* swap the value if necessary */ #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! if (size==4) val = swap_half_word((uint16_t)val); ! else if (size==2) val = swap_word(val); ! else val = val; #else ! val = val; #endif ! if (size==4) ! *reinterpret_cast<uint32_t *>(ptr) = val; ! else if (size==1) ! *ptr = (uint8_t)val; else if (size==2) ! *reinterpret_cast<uint16_t *>(ptr) = val; ! else { ! fprintf(stderr, "%s: illegal access size, must be 1, 2 or 4 - " ! "addr=%08x size=%d\n", cache<n_block,n_assoc,bsize>::name.c_str(), ! addr, size); ! } nWrites++; *************** *** 470,478 **** // remember the address ! waddr = addr/bsize*bsize; /* locate a block */ ! reqTag = allocateBlock(addr); ! reqLine = &values[0][0] + (reqTag - &tags[0][0]); // need to flush this line --- 475,483 ---- // remember the address ! aligned_addr = addr/bsize*bsize; /* locate a block */ ! reqTag = allocate_block(addr); ! reqLine = &values[0][0] + (reqTag - &cache<n_block,n_assoc,bsize>::tags[0][0]); // need to flush this line *************** *** 480,485 **** // get the address of the line ! uint32_t flush_index = (reqTag-&tags[0][0])/n_assoc; ! faddr = reconstruct_address(flush_index, reqTag->tag); flush_only = false; --- 485,490 ---- // get the address of the line ! uint32_t flush_index = (reqTag-&cache<n_block,n_assoc,bsize>::tags[0][0])/n_assoc; ! flush_addr = get_address(flush_index, reqTag->tag); flush_only = false; *************** *** 489,494 **** } else { ! biu.post_request(false, faddr, bsize, reqLine->data); ! delay_flag = true; update_state = WAITING_FLUSH; } --- 494,498 ---- } else { ! biu.post_request(false, flush_addr, bsize, reqLine->data); update_state = WAITING_FLUSH; } *************** *** 500,510 **** } else { ! biu.post_request(true, waddr, bsize, reqLine->data); ! delay_flag = true; update_state = WAITING_LOAD; } } ! reqTag->tag = tag(addr); reqTag->valid = true; --- 504,513 ---- } else { ! biu.post_request(true, aligned_addr, bsize, reqLine->data); update_state = WAITING_LOAD; } } ! reqTag->tag = get_tag(addr); reqTag->valid = true; *************** *** 520,528 **** /* if in cache, then update the cache line with data */ ! reqTag = lookup(addr); if (reqTag) { ! faddr = addr/bsize*bsize; ! reqLine = &values[0][0] + (reqTag - &tags[0][0]); flush_only = true; --- 523,531 ---- /* if in cache, then update the cache line with data */ ! reqTag = look_up(addr); if (reqTag) { ! flush_addr = addr/bsize*bsize; ! reqLine = &values[0][0] + (reqTag - &cache<n_block,n_assoc,bsize>::tags[0][0]); flush_only = true; *************** *** 533,538 **** } else { ! biu.post_request(false, faddr, bsize, reqLine->data); ! delay_flag = true; update_state = WAITING_FLUSH; } --- 536,540 ---- } else { ! biu.post_request(false, flush_addr, bsize, reqLine->data); update_state = WAITING_FLUSH; } *************** *** 544,566 **** } ! void updateOnClockTick() { ! // delay one cycle before checking biu, for timing correctness ! if (delay_flag) { ! delay_flag = false; ! return; ! } ! if (update_state!=NO_UPDATE && biu.get_ack()) { ! switch (update_state) { ! case PENDING_FLUSH: ! if (!biu.is_busy()) { ! biu.post_request(false, faddr, bsize, reqLine->data); ! delay_flag = true; ! update_state = WAITING_FLUSH; ! } ! break; ! case WAITING_FLUSH: reqLine->dirty = false; if (flush_only) { --- 546,562 ---- } ! void update_on_clock() { ! switch (update_state) { ! case PENDING_FLUSH: ! if (!biu.is_busy()) { ! biu.post_request(false, flush_addr, bsize, reqLine->data); ! update_state = WAITING_FLUSH; ! } ! break; ! case WAITING_FLUSH: ! if (biu.get_ack()) { reqLine->dirty = false; if (flush_only) { *************** *** 570,588 **** else update_state = PENDING_LOAD; ! // fall through here ! case PENDING_LOAD: ! if (!biu.is_busy()) { ! biu.post_request(true, waddr, bsize, reqLine->data); ! delay_flag = true; ! update_state = WAITING_LOAD; ! } ! break; ! case WAITING_LOAD: ! if (!biu.is_busy()) update_state = NO_UPDATE; ! break; ! case NO_UPDATE: // suppress gcc warning ! break; ! } } } --- 566,585 ---- else update_state = PENDING_LOAD; ! } ! // fall through here ! case PENDING_LOAD: ! if (!biu.is_busy()) { ! biu.post_request(true, aligned_addr, bsize, reqLine->data); ! update_state = WAITING_LOAD; ! } ! break; ! ! case WAITING_LOAD: ! if (biu.get_ack()) update_state = NO_UPDATE; ! break; ! ! case NO_UPDATE: // suppress gcc warning ! break; } } *************** *** 590,602 **** void PrintStats(FILE *fp) { ! fprintf(fp, "Total %s writes: ", name.c_str()); dump_int64(nWrites, fp); ! fprintf(fp, "\nTotal %s write misses: ", name.c_str()); dump_int64(nWriteMisses, fp); ! fprintf(fp, "\nTotal %s reads: ", name.c_str()); dump_int64(nReads, fp); ! fprintf(fp, "\nTotal %s read misses: ", name.c_str()); dump_int64(nReadMisses, fp); ! fprintf(fp, "\n%s hit ratio: %.3f%%\n", name.c_str(), 100.0*(nReads+nWrites-nReadMisses-nWriteMisses)/ (nReads+nWrites)); --- 587,599 ---- void PrintStats(FILE *fp) { ! fprintf(fp, "Total %s writes: ", cache<n_block,n_assoc,bsize>::name.c_str()); dump_int64(nWrites, fp); ! fprintf(fp, "\nTotal %s write misses: ", cache<n_block,n_assoc,bsize>::name.c_str()); dump_int64(nWriteMisses, fp); ! fprintf(fp, "\nTotal %s reads: ", cache<n_block,n_assoc,bsize>::name.c_str()); dump_int64(nReads, fp); ! fprintf(fp, "\nTotal %s read misses: ", cache<n_block,n_assoc,bsize>::name.c_str()); dump_int64(nReadMisses, fp); ! fprintf(fp, "\n%s hit ratio: %.3f%%\n", cache<n_block,n_assoc,bsize>::name.c_str(), 100.0*(nReads+nWrites-nReadMisses-nWriteMisses)/ (nReads+nWrites)); *************** *** 605,611 **** protected: bus_interface &biu; ! uint32_t wval; ! uint32_t waddr; ! uint32_t faddr; // flush addr enum { --- 602,607 ---- protected: bus_interface &biu; ! uint32_t aligned_addr; ! uint32_t flush_addr; // flush addr enum { *************** *** 620,624 **** uint64_t nWrites, nWriteMisses; - bool delay_flag; //delay querying the bus for one cycle bool flush_only; --- 616,619 ---- |
|
From: Wei Q. <wei...@us...> - 2005-09-20 01:30:47
|
Update of /cvsroot/simit-arm/simit-arm/emulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv19609 Modified Files: .cvsignore Log Message: fixes cvsignore file Index: .cvsignore =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/.cvsignore,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** .cvsignore 24 Sep 2004 03:11:01 -0000 1.1.1.1 --- .cvsignore 20 Sep 2005 01:30:40 -0000 1.2 *************** *** 3,7 **** Makefile.in ema ! ema_count nwfpe.h --- 3,7 ---- Makefile.in ema ! ema_lite nwfpe.h |
|
From: Wei Q. <wei...@us...> - 2005-09-20 01:29:02
|
Update of /cvsroot/simit-arm/simit-arm/simulator/src In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv19241/src Added Files: .cvsignore Log Message: added files permanently --- NEW FILE: .cvsignore --- define.cpp define.hpp fetch_oper_dec.cpp fetch_oper_dec.hpp fetch_oper_pat.def fetch_oper_pat.hpp fetch_oper_tab.cpp func.cpp mach_list.hpp machines.cpp machines.hpp mang_list.hpp |
|
From: Wei Q. <wei...@us...> - 2005-09-20 01:29:01
|
Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv19241 Modified Files: .cvsignore armsim.hpp main.cpp more_managers.cpp Log Message: added files permanently Index: .cvsignore =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/.cvsignore,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -C2 -d -r1.1.1.1 -r1.2 *** .cvsignore 24 Sep 2004 03:11:01 -0000 1.1.1.1 --- .cvsignore 20 Sep 2005 01:28:53 -0000 1.2 *************** *** 4,5 **** --- 4,6 ---- sim_arm sima + checker Index: more_managers.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/more_managers.cpp,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** more_managers.cpp 23 Aug 2005 19:47:52 -0000 1.4 --- more_managers.cpp 20 Sep 2005 01:28:53 -0000 1.5 *************** *** 119,123 **** _armsim->write_gpr(0, _armsim->get_procid()); break; ! case 515: // get cycle count { uint64_t c = _armsim->get_cycle_count(); --- 119,126 ---- _armsim->write_gpr(0, _armsim->get_procid()); break; ! case 515: // get processor num ! _armsim->write_gpr(0, _armsim->get_procnum()); ! break; ! case 516: // get cycle count { uint64_t c = _armsim->get_cycle_count(); *************** *** 126,130 **** break; } ! case 516: // get system cycle count { uint64_t c = _armsim->get_system_cycle_count(); --- 129,133 ---- break; } ! case 517: // get system cycle count { uint64_t c = _armsim->get_system_cycle_count(); *************** *** 133,140 **** break; } ! case 517: _armsim->set_clock_divider(_armsim->read_gpr(0)); break; ! case 518: _armsim->sleep(_armsim->read_gpr(0)); break; --- 136,143 ---- break; } ! case 518: _armsim->set_clock_divider(_armsim->read_gpr(0)); break; ! case 519: _armsim->sleep(_armsim->read_gpr(0)); break; Index: main.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/main.cpp,v retrieving revision 1.7 retrieving revision 1.8 diff -C2 -d -r1.7 -r1.8 *** main.cpp 23 Aug 2005 19:47:52 -0000 1.7 --- main.cpp 20 Sep 2005 01:28:53 -0000 1.8 *************** *** 120,124 **** #endif ! sima->set_procid(0); sima->run(max_cnum); --- 120,124 ---- #endif ! sima->set_procinfo(1<<16); sima->run(max_cnum); Index: armsim.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.hpp,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** armsim.hpp 23 Aug 2005 19:47:52 -0000 1.6 --- armsim.hpp 20 Sep 2005 01:28:53 -0000 1.7 *************** *** 230,235 **** // get the id of the processor ! void set_procid(unsigned id) {procid = id;} ! unsigned get_procid() const {return procid;} --- 230,236 ---- // get the id of the processor ! void set_procinfo(unsigned id) {procinfo = id;} ! unsigned get_procid() const {return procinfo&0xFFFF;} ! unsigned get_procnum() const {return (procinfo>>16)&0xFFFF;} *************** *** 268,272 **** enum status_t status; ! unsigned procid; uint64_t cycle_count; /* number of simulation cycles, divided*/ uint64_t system_cycle_count;/* number of undivided cycles */ --- 269,273 ---- enum status_t status; ! unsigned procinfo; uint64_t cycle_count; /* number of simulation cycles, divided*/ uint64_t system_cycle_count;/* number of undivided cycles */ |
|
From: Wei Q. <wei...@us...> - 2005-09-14 17:18:06
|
Update of /cvsroot/simit-arm/simit-arm In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv13079 Modified Files: configure.in Log Message: change configuration file Index: configure.in =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/configure.in,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** configure.in 14 Sep 2005 17:10:06 -0000 1.5 --- configure.in 14 Sep 2005 17:17:58 -0000 1.6 *************** *** 122,126 **** emulator/nwfpe/Makefile emulator/Makefile - emu_single/Makefile simulator/Makefile]) AC_OUTPUT --- 122,125 ---- |
|
From: Wei Q. <wei...@us...> - 2005-09-14 17:10:22
|
Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv10272/simulator Modified Files: Makefile.am armsim.cpp Log Message: some configuration changes Index: Makefile.am =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/Makefile.am,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** Makefile.am 23 Aug 2005 19:47:52 -0000 1.6 --- Makefile.am 14 Sep 2005 17:10:06 -0000 1.7 *************** *** 26,30 **** include_temp.hpp more_managers.hpp interface.hpp \ cache.h fetch_oper_dec.hpp mach_list.hpp \ ! biu.h machines.hpp parms.h mcu.h \ fetch_oper_pat.hpp fetch_oper_tab.hpp func.hpp \ $(top_builddir)/emulator/syscall.cpp \ --- 26,30 ---- include_temp.hpp more_managers.hpp interface.hpp \ cache.h fetch_oper_dec.hpp mach_list.hpp \ ! biu.h machines.hpp parms.h mcu.hpp \ fetch_oper_pat.hpp fetch_oper_tab.hpp func.hpp \ $(top_builddir)/emulator/syscall.cpp \ Index: armsim.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.cpp,v retrieving revision 1.8 retrieving revision 1.9 diff -C2 -d -r1.8 -r1.9 *** armsim.cpp 23 Aug 2005 19:47:52 -0000 1.8 --- armsim.cpp 14 Sep 2005 17:10:06 -0000 1.9 *************** *** 180,185 **** fprintf(fp, "Total cycles : "); dump_int64(cycle_count, fp); fprintf(fp, "\nEquivalent time on 206.4MHz host: %.4f sec.\n", ! (double)cycle_count/206438400.0); #ifdef EMUMEM_HASH --- 180,187 ---- fprintf(fp, "Total cycles : "); dump_int64(cycle_count, fp); + fprintf(fp, "\nTotal system cycles : "); + dump_int64(system_cycle_count, fp); fprintf(fp, "\nEquivalent time on 206.4MHz host: %.4f sec.\n", ! (double)system_cycle_count/206438400.0); #ifdef EMUMEM_HASH *************** *** 192,195 **** --- 194,202 ---- mem->get_page_count()); #endif + + if (!use_self_mem) { + biu->print_stats(fp); + } + } *************** *** 236,239 **** --- 243,248 ---- if (c_count==0) { + c_count = c_div; + /** Activate all OSMs in order. */ for (work_it=work_list.begin(); work_it!=work_list.end();) { *************** *** 282,286 **** syscall_update(); - c_count = c_div; } --- 291,294 ---- *************** *** 288,292 **** system_cycle_count++; ! // memory operates at normal speed otherwise bus will be clogged imcu->update_on_clock(); dmcu->update_on_clock(); --- 296,300 ---- system_cycle_count++; ! // memory operates at normal speed otherwise bus may be blocked imcu->update_on_clock(); dmcu->update_on_clock(); |
|
From: Wei Q. <wei...@us...> - 2005-09-14 17:10:14
|
Update of /cvsroot/simit-arm/simit-arm In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv10272 Modified Files: configure.in filelist Log Message: some configuration changes Index: filelist =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/filelist,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** filelist 23 Aug 2005 19:50:49 -0000 1.3 --- filelist 14 Sep 2005 17:10:06 -0000 1.4 *************** *** 1,7 **** - emu_single/armemul.cpp - emu_single/armemul.h - emu_single/debug.cpp - emu_single/main.cpp - emu_single/misc.h emulator/arm_dec.h emulator/coproc.h --- 1,2 ---- Index: configure.in =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/configure.in,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** configure.in 2 Feb 2005 17:10:39 -0000 1.4 --- configure.in 14 Sep 2005 17:10:06 -0000 1.5 *************** *** 3,7 **** AC_INIT(simulator/main.cpp) ! AM_INIT_AUTOMAKE(SimIt-ARM, 2.1) AM_CONFIG_HEADER(config.h:config.h.in) --- 3,7 ---- AC_INIT(simulator/main.cpp) ! AM_INIT_AUTOMAKE(SimIt-ARM, 3.0pre) AM_CONFIG_HEADER(config.h:config.h.in) |
|
From: Wei Q. <wei...@us...> - 2005-08-23 19:50:57
|
Update of /cvsroot/simit-arm/simit-arm In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv2531 Modified Files: filelist Log Message: added new files names to filelist Index: filelist =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/filelist,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** filelist 2 Feb 2005 06:42:05 -0000 1.2 --- filelist 23 Aug 2005 19:50:49 -0000 1.3 *************** *** 42,46 **** emulator/ldst.h emulator/nwfpe.cpp ! simulator/BIU.h simulator/cache.h simulator/define.cpp --- 42,48 ---- emulator/ldst.h emulator/nwfpe.cpp ! simulator/biu.h ! simulator/biu.cpp ! simulator/mcu.hpp simulator/cache.h simulator/define.cpp *************** *** 65,68 **** --- 67,71 ---- simulator/armsim.cpp simulator/armsim.hpp + simulator/checker.cpp libosm/aggr_type.hpp libosm/auto_decoder.hpp |
|
From: Wei Q. <wei...@us...> - 2005-08-23 19:49:04
|
Update of /cvsroot/simit-arm/simit-arm/emulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv2151 Modified Files: armemul.cpp armemul.h emumem.h ldst.cpp loader.cpp loader.h loadfpe.cpp misc.h nwfpe.cpp nwfpe.h.in syscall.cpp syscall.h util.cpp Log Message: many updates Index: nwfpe.h.in =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/nwfpe.h.in,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** nwfpe.h.in 20 May 2005 06:11:27 -0000 1.5 --- nwfpe.h.in 23 Aug 2005 19:48:56 -0000 1.6 *************** *** 13,17 **** #include <misc.h> ! #ifdef __COMPILE_SIMULATOR_ namespace simulator { class arm_simulator; --- 13,17 ---- #include <misc.h> ! #ifdef COMPILE_SIMULATOR namespace simulator { class arm_simulator; Index: loadfpe.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/loadfpe.cpp,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** loadfpe.cpp 21 May 2005 20:28:48 -0000 1.5 --- loadfpe.cpp 23 Aug 2005 19:48:56 -0000 1.6 *************** *** 4,8 **** #include "nwfpe.h" ! #ifdef __COMPILE_SIMULATOR_ #include "armsim.hpp" #else --- 4,8 ---- #include "nwfpe.h" ! #ifdef COMPILE_SIMULATOR #include "armsim.hpp" #else Index: syscall.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/syscall.h,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** syscall.h 20 May 2005 06:11:27 -0000 1.4 --- syscall.h 23 Aug 2005 19:48:56 -0000 1.5 *************** *** 21,25 **** ! #ifdef __COMPILE_SIMULATOR_ namespace simulator { class arm_simulator; --- 21,25 ---- ! #ifdef COMPILE_SIMULATOR namespace simulator { class arm_simulator; Index: misc.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/misc.h,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** misc.h 20 May 2005 06:11:27 -0000 1.6 --- misc.h 23 Aug 2005 19:48:56 -0000 1.7 *************** *** 146,149 **** --- 146,151 ---- void dump_int64_smart(uint64_t, FILE *); + int lmb32(unsigned val); + /*target endianness*/ #define TARGET_LITTLE_ENDIAN 1 Index: nwfpe.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/nwfpe.cpp,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** nwfpe.cpp 20 May 2005 06:11:27 -0000 1.5 --- nwfpe.cpp 23 Aug 2005 19:48:56 -0000 1.6 *************** *** 2,6 **** #include "nwfpe.h" ! #ifdef __COMPILE_SIMULATOR_ #include "armsim.hpp" #else --- 2,6 ---- #include "nwfpe.h" ! #ifdef COMPILE_SIMULATOR #include "armsim.hpp" #else *************** *** 42,46 **** /* restore CPSR */ ! #ifndef __COMPILE_SIMULATOR_ WRITE_CPSR(MEM_READ_WORD(fpe_stack+64)); #else --- 42,46 ---- /* restore CPSR */ ! #ifndef COMPILE_SIMULATOR WRITE_CPSR(MEM_READ_WORD(fpe_stack+64)); #else *************** *** 69,73 **** /* program counter set to the next instruction */ MEM_WRITE_WORD(fpe_stack+i*4, pc-4); ! #ifndef __COMPILE_SIMULATOR_ MEM_WRITE_WORD(fpe_stack+64, READ_CPSR); #else --- 69,73 ---- /* program counter set to the next instruction */ MEM_WRITE_WORD(fpe_stack+i*4, pc-4); ! #ifndef COMPILE_SIMULATOR MEM_WRITE_WORD(fpe_stack+64, READ_CPSR); #else *************** *** 84,88 **** WRITE_REG(15, FPE_ENTRY); ! #ifndef __COMPILE_SIMULATOR_ EMULATOR_STUB(fpe, inst); #endif --- 84,88 ---- WRITE_REG(15, FPE_ENTRY); ! #ifndef COMPILE_SIMULATOR EMULATOR_STUB(fpe, inst); #endif Index: armemul.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/armemul.cpp,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** armemul.cpp 20 May 2005 06:11:26 -0000 1.5 --- armemul.cpp 23 Aug 2005 19:48:56 -0000 1.6 *************** *** 2,5 **** --- 2,6 ---- #include <csignal> #include <cstdio> + #include <cassert> #include "armemul.h" #include "decode.h" *************** *** 58,61 **** --- 59,64 ---- init_devices(dev_master); + syscall_buf = NULL; + reset(); } *************** *** 66,69 **** --- 69,76 ---- close_devices(dev_master); delete dev_master; + + if (syscall_buf) { + free(syscall_buf); + } } *************** *** 79,82 **** --- 86,94 ---- in_fpe = false; status = ST_RESET; + + if (syscall_buf) { + free(syscall_buf); + syscall_buf = false; + } } *************** *** 165,168 **** --- 177,188 ---- } + void arm_emulator::step() + { + arm_inst_t inst; + inst = fetch_inst(get_pc()); + execute(inst, get_pc()); + icount++; + } + void arm_emulator::init_registers() { *************** *** 189,193 **** int i; - fprintf(fp, "\n"); for(i = 0; i < INST_TOTAL; i++) { if(counters[i] > 0) { --- 209,212 ---- *************** *** 219,220 **** --- 238,263 ---- fputs(" nullified\n", fp); } + + void arm_emulator::syscall_realloc_buf(unsigned size) + { + assert(syscall_buf!=NULL); + syscall_buf = realloc(syscall_buf, size); + if (syscall_buf==NULL) { + fprintf(stderr, "Error: Out of host memory when allocating %d" + " bytes for a system call.\n", size); + exit(-1); + } + } + + void arm_emulator::syscall_alloc_buf(unsigned size) + { + if (syscall_buf!=NULL) + free(syscall_buf); + + syscall_buf = malloc(size); + if (syscall_buf==NULL) { + fprintf(stderr, "Error: Out of host memory when reallocating %d" + " bytes for a system call.\n", size); + exit(-1); + } + } Index: ldst.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/ldst.cpp,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** ldst.cpp 20 May 2005 06:11:27 -0000 1.6 --- ldst.cpp 23 Aug 2005 19:48:56 -0000 1.7 *************** *** 537,541 **** { uint32_t start_addr, end_addr, address, i; ! int32_t j, pcount = popcount16(inst)*4; if (!PFLD && UFLD) { --- 537,541 ---- { uint32_t start_addr, end_addr, address, i; ! int32_t pcount = popcount16(inst)*4; if (!PFLD && UFLD) { *************** *** 561,568 **** /*ignore the last two bits of the address*/ ! address = end_addr - (end_addr & 0x3); ! j = inst<<16; i=15; ! while (j) { ! if (j<0) { word_t val; --- 561,568 ---- /*ignore the last two bits of the address*/ ! address = start_addr-(start_addr&0x3); ! i=0; ! while (i<16) { ! if (inst&(1<<i)) { word_t val; *************** *** 570,579 **** val = MEM_READ_WORD(address); WRITE_REG(i, val); ! address -= 4; } ! j = j<<1; i--; } ! assert(start_addr-(start_addr&0x3) == address+4); if (BITn(inst, 15) & BITn(inst, 22)) WRITE_CPSR(SPSR); --- 570,579 ---- val = MEM_READ_WORD(address); WRITE_REG(i, val); ! address += 4; } ! i++; } ! assert(address == end_addr - (end_addr & 0x3) + 4); if (BITn(inst, 15) & BITn(inst, 22)) WRITE_CPSR(SPSR); *************** *** 585,589 **** { uint32_t start_addr, end_addr, address, i; ! int32_t j, pcount = popcount16(inst)*4; if (!PFLD && UFLD) { --- 585,589 ---- { uint32_t start_addr, end_addr, address, i; ! int32_t pcount = popcount16(inst)*4; if (!PFLD && UFLD) { *************** *** 609,624 **** /*ignore the last two bits of the address*/ ! address = end_addr - (end_addr & 0x3); ! j = inst<<16; i=15; ! while (j) { ! if (j<0) { word_t val=READ_REG(i); MEM_WRITE_WORD(address, val); /*MEM_WRITE_WORD(address, READ_REG(i));*/ ! address -= 4; } ! j = j<<1; i--; } ! assert(start_addr - (start_addr&0x3) == address+4); EMULATOR_STUB(stm,inst); --- 609,624 ---- /*ignore the last two bits of the address*/ ! address = start_addr - (start_addr&0x3); ! i=0; ! while (i<16) { ! if (inst&(1<<i)) { word_t val=READ_REG(i); MEM_WRITE_WORD(address, val); /*MEM_WRITE_WORD(address, READ_REG(i));*/ ! address += 4; } ! i++; } ! assert(address == (end_addr - (end_addr & 0x3) + 4)); EMULATOR_STUB(stm,inst); Index: syscall.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/syscall.cpp,v retrieving revision 1.7 retrieving revision 1.8 diff -C2 -d -r1.7 -r1.8 *** syscall.cpp 20 May 2005 06:11:27 -0000 1.7 --- syscall.cpp 23 Aug 2005 19:48:56 -0000 1.8 *************** *** 1,18 **** /*************************************************************************** ! syscall.c - description ! ------------------- ! begin : Wed Sep 26 2001 ! copyright : (C) 2001 CEA and Université Paris XI Orsay ! author : Gilles Mouchard ! email : gil...@lr..., gil...@ce... ***************************************************************************/ /*************************************************************************** [...1403 lines suppressed...] ! memcpy(emu->syscall_buf, &buf, sizeof(struct stat64)); ! MEM_WRITE_BLOCK(buf_addr, emu->syscall_buf, sizeof(struct stat64)); } ! ! SYSCALL_ADV_STAGE ! } ! ! SYSCALL_STAGE_1 ! { ! SYSCALL_RESET_STAGE ! RETURN(emu->syscall_iret); ! return emu->syscall_iret != -1; ! } ! ! SYSCALL_STAGE_FALSE ! #else ! RETURN(-1); return false; #endif Index: emumem.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/emumem.h,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** emumem.h 20 May 2005 06:11:27 -0000 1.6 --- emumem.h 23 Aug 2005 19:48:56 -0000 1.7 *************** *** 11,15 **** #endif ! // exclusive option #ifdef EMUMEM_FAST #undef EMUMEM_SAFE --- 11,15 ---- #endif ! // exclusive options, either fast or safe #ifdef EMUMEM_FAST #undef EMUMEM_SAFE Index: util.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/util.cpp,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** util.cpp 12 Nov 2004 06:32:59 -0000 1.2 --- util.cpp 23 Aug 2005 19:48:56 -0000 1.3 *************** *** 69,70 **** --- 69,79 ---- } + /* get the position of the left most bit of an integer, from 0-31, -1 for 0 */ + int lmb32(unsigned val) + { + int ii; + for (ii=31; ii>=0; ii++) + if (val&(1u<<ii)) return ii; + + return 0; + } Index: loader.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/loader.cpp,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** loader.cpp 20 May 2005 06:11:27 -0000 1.4 --- loader.cpp 23 Aug 2005 19:48:56 -0000 1.5 *************** *** 20,24 **** #include "loader.h" ! #ifdef __COMPILE_SIMULATOR_ #include "armsim.hpp" #else --- 20,24 ---- #include "loader.h" ! #ifdef COMPILE_SIMULATOR #include "armsim.hpp" #else *************** *** 208,214 **** abrk -= abrk % 4096; ! set_brk(abrk); ! set_mmap_brk(MMAP_BASE); fname_cache = filename; --- 208,214 ---- abrk -= abrk % 4096; ! syscall_set_brk(abrk); ! syscall_set_mmap_brk(MMAP_BASE); fname_cache = filename; Index: armemul.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/armemul.h,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** armemul.h 20 May 2005 06:11:26 -0000 1.5 --- armemul.h 23 Aug 2005 19:48:56 -0000 1.6 *************** *** 71,74 **** --- 71,76 ---- void debug(); + /* fetch and run one instruction */ + void step(); *************** *** 110,120 **** /* some system-call library variables */ ! arm_addr_t get_brk() const {return brk_point;} ! arm_addr_t get_mmap_brk() const {return mmap_brk_point;} /* set brk point for syscall emulation */ ! void set_brk(arm_addr_t addr) {brk_point = addr;} ! void set_mmap_brk(arm_addr_t addr) {mmap_brk_point = addr;} --- 112,124 ---- /* some system-call library variables */ ! arm_addr_t syscall_get_brk() const {return brk_point;} ! arm_addr_t syscall_get_mmap_brk() const {return mmap_brk_point;} /* set brk point for syscall emulation */ ! void syscall_set_brk(arm_addr_t addr) {brk_point = addr;} ! void syscall_set_mmap_brk(arm_addr_t addr) {mmap_brk_point = addr;} + void syscall_alloc_buf(unsigned size); + void syscall_realloc_buf(unsigned size); *************** *** 165,168 **** --- 169,185 ---- + /* some scratch variables for system call */ + int syscall_phase; + + // temporary variables for syscall.cpp to use + int syscall_iret; + void *syscall_buf; + + unsigned syscall_mem_size; + int syscall_open_len; + int syscall_open_addr; + int syscall_times_ret; + + private: Index: loader.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/loader.h,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** loader.h 12 Nov 2004 06:32:59 -0000 1.2 --- loader.h 23 Aug 2005 19:48:56 -0000 1.3 *************** *** 21,25 **** ! #ifdef __COMPILE_SIMULATOR_ namespace simulator { class arm_simulator; --- 21,25 ---- ! #ifdef COMPILE_SIMULATOR namespace simulator { class arm_simulator; |
|
From: Wei Q. <wei...@us...> - 2005-08-23 19:48:09
|
Update of /cvsroot/simit-arm/simit-arm/simulator/src In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv1880/src Modified Files: arm.mad ldst.mad Log Message: added support for smp simulation, implemented swp swpb instructions Index: ldst.mad =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/src/ldst.mad,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** ldst.mad 2 Feb 2005 17:53:35 -0000 1.4 --- ldst.mad 23 Aug 2005 19:47:52 -0000 1.5 *************** *** 35,39 **** off_str = imm.dec; +opcd; ! mode = mem_size << 1; TRANS --- 35,39 ---- off_str = imm.dec; +opcd; ! mode = (mem_size << 2) | 2; TRANS *************** *** 76,80 **** off_str = shift.syn; +opcd; ! mode = mem_size << 1; TRANS --- 76,80 ---- off_str = shift.syn; +opcd; ! mode = (mem_size << 2) | 2; TRANS *************** *** 124,128 **** +opcd; m_size = h_uint?2:1; ! mode = h_uint?4:2; TRANS --- 124,128 ---- +opcd; m_size = h_uint?2:1; ! mode = h_uint?10:6; TRANS *************** *** 176,180 **** +opcd; m_size = h_uint?2:1; ! mode = h_uint?4:2; TRANS --- 176,180 ---- +opcd; m_size = h_uint?2:1; ! mode = h_uint?10:6; TRANS *************** *** 227,231 **** off_str = imm.dec; +opcd; ! mode = (mem_size << 1) | 1; TRANS --- 227,231 ---- off_str = imm.dec; +opcd; ! mode = (mem_size << 2) | 1; TRANS *************** *** 268,272 **** off_str = shift.syn; +opcd; ! mode = (mem_size << 1) | 1; TRANS --- 268,272 ---- off_str = shift.syn; +opcd; ! mode = (mem_size << 2) | 1; TRANS *************** *** 315,319 **** +opcd; m_size = h_uint?2:1; ! mode = h_uint?5:3; TRANS --- 315,319 ---- +opcd; m_size = h_uint?2:1; ! mode = h_uint?9:5; TRANS *************** *** 361,365 **** +opcd; m_size = h_uint?2:1; ! mode = h_uint?5:3; TRANS --- 361,365 ---- +opcd; m_size = h_uint?2:1; ! mode = h_uint?9:5; TRANS *************** *** 562,572 **** e_ex_bf: {pred>0, bf_buffer = mBF[], !ex_buffer, ! *mMemAddr[] = v_rn, *mMemCtrl[] = 8}; ! e_bf_bf_post: {*mMemCtrl[], v_rd = *mMemRead[], ! *mMemWrite[] = v_rm, *mMemCtrl[] = 9}; ! e_bf_post_wb: {*mMemCtrl[], wb_buffer = mWB[], !bf_buffer, ! *dst_buffer = v_rd, !dst_buffer, *mReset[]=(rd,1)}; e_wb_in: {!wb_buffer}; --- 562,598 ---- e_ex_bf: {pred>0, bf_buffer = mBF[], !ex_buffer, ! *mMemAddr[] = v_rn, *mMemWrite[] = v_rm, *mMemCtrl[] = 19}; ! e_bf_wb: {wb_buffer = mWB[], !bf_buffer, *mMemCtrl[], ! *dst_buffer = *mMemRead[], !dst_buffer, *mReset[]=(rd,1)}; ! e_wb_in: {!wb_buffer}; ! ! e_ex_bf_null: {pred==0, bf_buffer = mBF[], !!ex_buffer, !!dst_buffer}; ! e_bf_wb_null: {wb_buffer = mWB[], !!bf_buffer}; ! e_wb_in_null: {!!wb_buffer}; ! ! e_ex_in: {*mReset[], !!ex_buffer, !!dst_buffer}; ! ! ! OPERATION swapb ! ! SYNTAX "swp" ^ cond_names[cond] ^ "b" reg_names[rd]^"," reg_names[rn]^", [" ! reg_names[rn]^"]"; ! CODING cond 000101 00 rn rd 0000 1001 rm ; ! ! TRANS ! e_id_ex: {ex_buffer = mEX[], !id_buffer, ! v_rm = *mRF[rm], v_rn = *mRF[rn], dst_buffer = mRF[rd], ! v_iflag = *mCPSR[]} ! ! eval_pred(pred, cond, v_iflag); ! ! e_ex_bf: {pred>0, ! bf_buffer = mBF[], !ex_buffer, ! *mMemAddr[] = v_rn, *mMemWrite[] = v_rm, *mMemCtrl[] = 7}; ! ! e_bf_wb: {wb_buffer = mWB[], !bf_buffer, *mMemCtrl[], ! *dst_buffer = *mMemRead[], !dst_buffer, *mReset[]=(rd,1)}; e_wb_in: {!wb_buffer}; *************** *** 647,651 **** rmb(i0, rinds, 0); popcount16(bcount, rinds); ! mode = (bcount << 4) | 8; +wbit; --- 673,677 ---- rmb(i0, rinds, 0); popcount16(bcount, rinds); ! mode = (bcount << 5) | 18; +wbit; *************** *** 815,819 **** rmb(i14, rinds, i0+1); popcount16(bcount, rinds); ! mode = (bcount << 4) | 9; +wbit; --- 841,845 ---- rmb(i14, rinds, i0+1); popcount16(bcount, rinds); ! mode = (bcount << 5) | 17; +wbit; *************** *** 947,949 **** e_wb_in: {!wb_buffer}; - --- 973,974 ---- Index: arm.mad =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/src/arm.mad,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** arm.mad 19 Aug 2005 03:15:07 -0000 1.3 --- arm.mad 23 Aug 2005 19:47:52 -0000 1.4 *************** *** 77,81 **** mem_read_port : void -> uint<32>; mem_write_port : void -> uint<32>; ! mem_ctrl_port : void -> uint<32>; # count :: size(3bit) :: r/w (1bit) # new pc, written by branch operation --- 77,81 ---- mem_read_port : void -> uint<32>; mem_write_port : void -> uint<32>; ! mem_ctrl_port : void -> uint<32>; # count :: size(3bit) :: r :: w # new pc, written by branch operation *************** *** 263,267 **** load_imm, load_reg, load_ext_imm, load_ext_reg, store_imm, store_reg, store_ext_imm, store_ext_reg, ! swap, ldm, stm, mult, mult_long, syscall, coproc_inst}(unknown); # unknown as the default --- 263,267 ---- load_imm, load_reg, load_ext_imm, load_ext_reg, store_imm, store_reg, store_ext_imm, store_ext_reg, ! swap, swapb, ldm, stm, mult, mult_long, syscall, coproc_inst}(unknown); # unknown as the default |
|
From: Wei Q. <wei...@us...> - 2005-08-23 19:48:05
|
Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv1880 Modified Files: Makefile.am armsim.cpp armsim.hpp biu.cpp cache.h fetch_oper_pat.hpp fetch_oper_tab.hpp machines.cpp machines.hpp main.cpp mcu.hpp more_managers.cpp more_managers.hpp Added Files: biu.h Log Message: added support for smp simulation, implemented swp swpb instructions Index: machines.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/machines.hpp,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** machines.hpp 19 Aug 2005 03:15:05 -0000 1.3 --- machines.hpp 23 Aug 2005 19:47:52 -0000 1.4 *************** *** 1135,1254 **** L_$S_EX$36821, /*1121*/ L_$S_BF$36823, /*1122*/ ! L_$S_BF_POST$36841, /*1123*/ ! L_$S_ID$36890, /*1124*/ ! L_$S_EX$36891, /*1125*/ ! L_$S_B0$36895, /*1126*/ ! L_$S_B2$36896, /*1127*/ ! L_$S_B3$36897, /*1128*/ ! L_$S_B4$36898, /*1129*/ ! L_$S_B5$36899, /*1130*/ ! L_$S_B6$36900, /*1131*/ ! L_$S_B7$36901, /*1132*/ ! L_$S_B8$36902, /*1133*/ ! L_$S_B9$36903, /*1134*/ ! L_$S_B10$36904, /*1135*/ ! L_$S_B11$36905, /*1136*/ ! L_$S_B12$36906, /*1137*/ ! L_$S_B13$36907, /*1138*/ ! L_$S_B14$36908, /*1139*/ ! L_$S_B15$36909, /*1140*/ ! L_$S_B1$36913, /*1141*/ ! L_$S_ID$36960, /*1142*/ ! L_$S_EX$36961, /*1143*/ ! L_$S_B0$36965, /*1144*/ ! L_$S_B2$36966, /*1145*/ ! L_$S_B3$36967, /*1146*/ ! L_$S_B4$36968, /*1147*/ ! L_$S_B5$36969, /*1148*/ ! L_$S_B6$36970, /*1149*/ ! L_$S_B7$36971, /*1150*/ ! L_$S_B8$36972, /*1151*/ ! L_$S_B9$36973, /*1152*/ ! L_$S_B10$36974, /*1153*/ ! L_$S_B11$36975, /*1154*/ ! L_$S_B12$36976, /*1155*/ ! L_$S_B13$36977, /*1156*/ ! L_$S_B14$36978, /*1157*/ ! L_$S_B15$36979, /*1158*/ ! L_$S_ID$37030, /*1159*/ ! L_$S_EX$37031, /*1160*/ ! L_$S_B0$37035, /*1161*/ ! L_$S_B2$37036, /*1162*/ ! L_$S_B3$37037, /*1163*/ ! L_$S_B4$37038, /*1164*/ ! L_$S_B5$37039, /*1165*/ ! L_$S_B6$37040, /*1166*/ ! L_$S_B7$37041, /*1167*/ ! L_$S_B8$37042, /*1168*/ ! L_$S_B9$37043, /*1169*/ ! L_$S_B10$37044, /*1170*/ ! L_$S_B11$37045, /*1171*/ ! L_$S_B12$37046, /*1172*/ ! L_$S_B13$37047, /*1173*/ ! L_$S_B14$37048, /*1174*/ ! L_$S_B15$37049, /*1175*/ ! L_$S_B1$37053, /*1176*/ ! L_$S_ID$37100, /*1177*/ ! L_$S_EX$37101, /*1178*/ ! L_$S_B0$37105, /*1179*/ ! L_$S_B2$37106, /*1180*/ ! L_$S_B3$37107, /*1181*/ ! L_$S_B4$37108, /*1182*/ ! L_$S_B5$37109, /*1183*/ ! L_$S_B6$37110, /*1184*/ ! L_$S_B7$37111, /*1185*/ ! L_$S_B8$37112, /*1186*/ ! L_$S_B9$37113, /*1187*/ ! L_$S_B10$37114, /*1188*/ ! L_$S_B11$37115, /*1189*/ ! L_$S_B12$37116, /*1190*/ ! L_$S_B13$37117, /*1191*/ ! L_$S_B14$37118, /*1192*/ ! L_$S_B15$37119, /*1193*/ ! L_$S_ID$37170, /*1194*/ ! L_$S_EX$37171, /*1195*/ ! L_$S_BF$37173, /*1196*/ ! L_$S_BF_NULL$37174, /*1197*/ ! L_$S_WB_NULL$37192, /*1198*/ ! L_$S_ID$37240, /*1199*/ ! L_$S_EX$37241, /*1200*/ ! L_$S_ID$37310, /*1201*/ ! L_$S_EX$37311, /*1202*/ ! L_$S_ID$37380, /*1203*/ ! L_$S_EX$37381, /*1204*/ ! L_$S_ID$37450, /*1205*/ ! L_$S_EX$37451, /*1206*/ ! L_$S_BF$37453, /*1207*/ ! L_$S_BF_POST$37471, /*1208*/ ! L_$S_ID$37520, /*1209*/ ! L_$S_EX$37521, /*1210*/ ! L_$S_BF$37523, /*1211*/ ! L_$S_ID$37590, /*1212*/ ! L_$S_EX$37591, /*1213*/ ! L_$S_ID$37660, /*1214*/ ! L_$S_EX$37661, /*1215*/ ! L_$S_ID$37730, /*1216*/ ! L_$S_EX$37731, /*1217*/ ! L_$S_ID$37800, /*1218*/ ! L_$S_EX$37801, /*1219*/ ! L_$S_ID$37870, /*1220*/ ! L_$S_EX$37871, /*1221*/ ! L_$S_ID$37940, /*1222*/ ! L_$S_EX$37941, /*1223*/ ! L_$S_ID$38010, /*1224*/ ! L_$S_EX$38011, /*1225*/ ! L_$S_BF$38013, /*1226*/ ! L_$S_WB$38030, /*1227*/ ! L_$S_ID$38080, /*1228*/ ! L_$S_EX$38081, /*1229*/ ! L_$S_BF$38083, /*1230*/ ! L_$S_WB$38100, /*1231*/ ! L_$S_ID$38150, /*1232*/ L_$S_ID$38220, /*1233*/ L_$S_ID$38290, /*1234*/ L_$S_ID$38360, /*1235*/ L_$S_ID$38430, /*1236*/ ! L_$S_EX$38431, /*1237*/ ! L_$S_BF$38433, /*1238*/ }; --- 1135,1255 ---- L_$S_EX$36821, /*1121*/ L_$S_BF$36823, /*1122*/ ! L_$S_ID$36890, /*1123*/ ! L_$S_EX$36891, /*1124*/ ! L_$S_ID$36960, /*1125*/ ! L_$S_EX$36961, /*1126*/ ! L_$S_B0$36965, /*1127*/ ! L_$S_B2$36966, /*1128*/ ! L_$S_B3$36967, /*1129*/ ! L_$S_B4$36968, /*1130*/ ! L_$S_B5$36969, /*1131*/ ! L_$S_B6$36970, /*1132*/ ! L_$S_B7$36971, /*1133*/ ! L_$S_B8$36972, /*1134*/ ! L_$S_B9$36973, /*1135*/ ! L_$S_B10$36974, /*1136*/ ! L_$S_B11$36975, /*1137*/ ! L_$S_B12$36976, /*1138*/ ! L_$S_B13$36977, /*1139*/ ! L_$S_B14$36978, /*1140*/ ! L_$S_B15$36979, /*1141*/ ! L_$S_B1$36983, /*1142*/ ! L_$S_ID$37030, /*1143*/ ! L_$S_EX$37031, /*1144*/ ! L_$S_B0$37035, /*1145*/ ! L_$S_B2$37036, /*1146*/ ! L_$S_B3$37037, /*1147*/ ! L_$S_B4$37038, /*1148*/ ! L_$S_B5$37039, /*1149*/ ! L_$S_B6$37040, /*1150*/ ! L_$S_B7$37041, /*1151*/ ! L_$S_B8$37042, /*1152*/ ! L_$S_B9$37043, /*1153*/ ! L_$S_B10$37044, /*1154*/ ! L_$S_B11$37045, /*1155*/ ! L_$S_B12$37046, /*1156*/ ! L_$S_B13$37047, /*1157*/ ! L_$S_B14$37048, /*1158*/ ! L_$S_B15$37049, /*1159*/ ! L_$S_ID$37100, /*1160*/ ! L_$S_EX$37101, /*1161*/ ! L_$S_B0$37105, /*1162*/ ! L_$S_B2$37106, /*1163*/ ! L_$S_B3$37107, /*1164*/ ! L_$S_B4$37108, /*1165*/ ! L_$S_B5$37109, /*1166*/ ! L_$S_B6$37110, /*1167*/ ! L_$S_B7$37111, /*1168*/ ! L_$S_B8$37112, /*1169*/ ! L_$S_B9$37113, /*1170*/ ! L_$S_B10$37114, /*1171*/ ! L_$S_B11$37115, /*1172*/ ! L_$S_B12$37116, /*1173*/ ! L_$S_B13$37117, /*1174*/ ! L_$S_B14$37118, /*1175*/ ! L_$S_B15$37119, /*1176*/ ! L_$S_B1$37123, /*1177*/ ! L_$S_ID$37170, /*1178*/ ! L_$S_EX$37171, /*1179*/ ! L_$S_B0$37175, /*1180*/ ! L_$S_B2$37176, /*1181*/ ! L_$S_B3$37177, /*1182*/ ! L_$S_B4$37178, /*1183*/ ! L_$S_B5$37179, /*1184*/ ! L_$S_B6$37180, /*1185*/ ! L_$S_B7$37181, /*1186*/ ! L_$S_B8$37182, /*1187*/ ! L_$S_B9$37183, /*1188*/ ! L_$S_B10$37184, /*1189*/ ! L_$S_B11$37185, /*1190*/ ! L_$S_B12$37186, /*1191*/ ! L_$S_B13$37187, /*1192*/ ! L_$S_B14$37188, /*1193*/ ! L_$S_B15$37189, /*1194*/ ! L_$S_ID$37240, /*1195*/ ! L_$S_EX$37241, /*1196*/ ! L_$S_BF$37243, /*1197*/ ! L_$S_BF_NULL$37244, /*1198*/ ! L_$S_WB_NULL$37262, /*1199*/ ! L_$S_ID$37310, /*1200*/ ! L_$S_EX$37311, /*1201*/ ! L_$S_ID$37380, /*1202*/ ! L_$S_EX$37381, /*1203*/ ! L_$S_ID$37450, /*1204*/ ! L_$S_EX$37451, /*1205*/ ! L_$S_ID$37520, /*1206*/ ! L_$S_EX$37521, /*1207*/ ! L_$S_BF$37523, /*1208*/ ! L_$S_BF_POST$37541, /*1209*/ ! L_$S_ID$37590, /*1210*/ ! L_$S_EX$37591, /*1211*/ ! L_$S_BF$37593, /*1212*/ ! L_$S_ID$37660, /*1213*/ ! L_$S_EX$37661, /*1214*/ ! L_$S_ID$37730, /*1215*/ ! L_$S_EX$37731, /*1216*/ ! L_$S_ID$37800, /*1217*/ ! L_$S_EX$37801, /*1218*/ ! L_$S_ID$37870, /*1219*/ ! L_$S_EX$37871, /*1220*/ ! L_$S_ID$37940, /*1221*/ ! L_$S_EX$37941, /*1222*/ ! L_$S_ID$38010, /*1223*/ ! L_$S_EX$38011, /*1224*/ ! L_$S_ID$38080, /*1225*/ ! L_$S_EX$38081, /*1226*/ ! L_$S_BF$38083, /*1227*/ ! L_$S_WB$38100, /*1228*/ ! L_$S_ID$38150, /*1229*/ ! L_$S_EX$38151, /*1230*/ ! L_$S_BF$38153, /*1231*/ ! L_$S_WB$38170, /*1232*/ L_$S_ID$38220, /*1233*/ L_$S_ID$38290, /*1234*/ L_$S_ID$38360, /*1235*/ L_$S_ID$38430, /*1236*/ ! L_$S_ID$38500, /*1237*/ ! L_$S_EX$38501, /*1238*/ ! L_$S_BF$38503, /*1239*/ }; *************** *** 1779,1882 **** bool L_$e_id_ex$36845(); bool L_$e_ex_bf$36849(); ! bool L_$e_bf_bf_post$36869(); ! bool L_$e_bf_post_wb$36887(); bool L_$e_id_ex$36915(); - bool L_$e_ex_in$36918(); bool L_$e_ex_bf$36919(); - bool L_$e_ex_bf_null$36920(); - bool L_$e_ex_b0$36921(); - bool L_$e_ex_b2$36922(); - bool L_$e_ex_b3$36923(); - bool L_$e_ex_b4$36924(); - bool L_$e_ex_b5$36925(); - bool L_$e_ex_b6$36926(); - bool L_$e_ex_b7$36927(); - bool L_$e_ex_b8$36928(); - bool L_$e_ex_b9$36929(); - bool L_$e_ex_b10$36930(); - bool L_$e_ex_b11$36931(); - bool L_$e_ex_b12$36932(); - bool L_$e_ex_b13$36933(); - bool L_$e_ex_b14$36934(); - bool L_$e_ex_b15$36935(); - bool L_$e_b0_bf$36941(); - bool L_$e_b2_b1$36942(); - bool L_$e_b3_b2$36943(); - bool L_$e_b4_b3$36944(); - bool L_$e_b5_b4$36945(); - bool L_$e_b6_b5$36946(); - bool L_$e_b7_b6$36947(); - bool L_$e_b8_b7$36948(); - bool L_$e_b9_b8$36949(); - bool L_$e_b10_b9$36950(); - bool L_$e_b11_b10$36951(); - bool L_$e_b12_b11$36952(); - bool L_$e_b13_b12$36953(); - bool L_$e_b14_b13$36954(); - bool L_$e_b15_b14$36955(); - bool L_$e_b1_wb$36959(); bool L_$e_id_ex$36985(); bool L_$e_ex_in$36988(); bool L_$e_ex_bf$36989(); bool L_$e_ex_bf_null$36990(); bool L_$e_b0_bf$37011(); bool L_$e_b2_b1$37012(); bool L_$e_id_ex$37055(); bool L_$e_ex_bf$37059(); ! bool L_$e_ex_b0$37061(); ! bool L_$e_ex_b2$37062(); ! bool L_$e_ex_b3$37063(); ! bool L_$e_ex_b4$37064(); ! bool L_$e_ex_b5$37065(); ! bool L_$e_ex_b6$37066(); ! bool L_$e_ex_b7$37067(); ! bool L_$e_ex_b8$37068(); ! bool L_$e_ex_b9$37069(); ! bool L_$e_ex_b10$37070(); ! bool L_$e_ex_b11$37071(); ! bool L_$e_ex_b12$37072(); ! bool L_$e_ex_b13$37073(); ! bool L_$e_ex_b14$37074(); ! bool L_$e_ex_b15$37075(); bool L_$e_b0_bf$37081(); bool L_$e_b2_b1$37082(); - bool L_$e_b3_b2$37083(); - bool L_$e_b4_b3$37084(); - bool L_$e_b5_b4$37085(); - bool L_$e_b6_b5$37086(); - bool L_$e_b7_b6$37087(); - bool L_$e_b8_b7$37088(); - bool L_$e_b9_b8$37089(); - bool L_$e_b10_b9$37090(); - bool L_$e_b11_b10$37091(); - bool L_$e_b12_b11$37092(); - bool L_$e_b13_b12$37093(); - bool L_$e_b14_b13$37094(); - bool L_$e_b15_b14$37095(); - bool L_$e_b1_wb$37099(); bool L_$e_id_ex$37125(); bool L_$e_ex_bf$37129(); bool L_$e_b0_bf$37151(); bool L_$e_b2_b1$37152(); bool L_$e_id_ex$37195(); - bool L_$e_ex_in$37198(); bool L_$e_ex_bf$37199(); ! bool L_$e_bf_wb$37218(); ! bool L_$e_bf_wb_null$37220(); ! bool L_$e_wb_in_null$37238(); bool L_$e_ex_bf$37269(); ! bool L_$e_id_ex$37335(); bool L_$e_ex_bf$37339(); bool L_$e_ex_bf$37409(); - bool L_$e_id_ex$37475(); - bool L_$e_ex_in$37478(); bool L_$e_ex_bf$37479(); ! bool L_$e_ex_bf_null$37480(); ! bool L_$e_bf_bf_post$37499(); ! bool L_$e_bf_post_wb$37517(); bool L_$e_ex_bf$37549(); bool L_$e_bf_bf_post$37569(); ! bool L_$e_id_ex$37615(); bool L_$e_ex_bf$37619(); bool L_$e_ex_bf$37689(); bool L_$e_ex_bf$37759(); --- 1780,1883 ---- bool L_$e_id_ex$36845(); bool L_$e_ex_bf$36849(); ! bool L_$e_bf_wb$36868(); bool L_$e_id_ex$36915(); bool L_$e_ex_bf$36919(); bool L_$e_id_ex$36985(); bool L_$e_ex_in$36988(); bool L_$e_ex_bf$36989(); bool L_$e_ex_bf_null$36990(); + bool L_$e_ex_b0$36991(); + bool L_$e_ex_b2$36992(); + bool L_$e_ex_b3$36993(); + bool L_$e_ex_b4$36994(); + bool L_$e_ex_b5$36995(); + bool L_$e_ex_b6$36996(); + bool L_$e_ex_b7$36997(); + bool L_$e_ex_b8$36998(); + bool L_$e_ex_b9$36999(); + bool L_$e_ex_b10$37000(); + bool L_$e_ex_b11$37001(); + bool L_$e_ex_b12$37002(); + bool L_$e_ex_b13$37003(); + bool L_$e_ex_b14$37004(); + bool L_$e_ex_b15$37005(); bool L_$e_b0_bf$37011(); bool L_$e_b2_b1$37012(); + bool L_$e_b3_b2$37013(); + bool L_$e_b4_b3$37014(); + bool L_$e_b5_b4$37015(); + bool L_$e_b6_b5$37016(); + bool L_$e_b7_b6$37017(); + bool L_$e_b8_b7$37018(); + bool L_$e_b9_b8$37019(); + bool L_$e_b10_b9$37020(); + bool L_$e_b11_b10$37021(); + bool L_$e_b12_b11$37022(); + bool L_$e_b13_b12$37023(); + bool L_$e_b14_b13$37024(); + bool L_$e_b15_b14$37025(); + bool L_$e_b1_wb$37029(); bool L_$e_id_ex$37055(); + bool L_$e_ex_in$37058(); bool L_$e_ex_bf$37059(); ! bool L_$e_ex_bf_null$37060(); bool L_$e_b0_bf$37081(); bool L_$e_b2_b1$37082(); bool L_$e_id_ex$37125(); bool L_$e_ex_bf$37129(); + bool L_$e_ex_b0$37131(); + bool L_$e_ex_b2$37132(); + bool L_$e_ex_b3$37133(); + bool L_$e_ex_b4$37134(); + bool L_$e_ex_b5$37135(); + bool L_$e_ex_b6$37136(); + bool L_$e_ex_b7$37137(); + bool L_$e_ex_b8$37138(); + bool L_$e_ex_b9$37139(); + bool L_$e_ex_b10$37140(); + bool L_$e_ex_b11$37141(); + bool L_$e_ex_b12$37142(); + bool L_$e_ex_b13$37143(); + bool L_$e_ex_b14$37144(); + bool L_$e_ex_b15$37145(); bool L_$e_b0_bf$37151(); bool L_$e_b2_b1$37152(); + bool L_$e_b3_b2$37153(); + bool L_$e_b4_b3$37154(); + bool L_$e_b5_b4$37155(); + bool L_$e_b6_b5$37156(); + bool L_$e_b7_b6$37157(); + bool L_$e_b8_b7$37158(); + bool L_$e_b9_b8$37159(); + bool L_$e_b10_b9$37160(); + bool L_$e_b11_b10$37161(); + bool L_$e_b12_b11$37162(); + bool L_$e_b13_b12$37163(); + bool L_$e_b14_b13$37164(); + bool L_$e_b15_b14$37165(); + bool L_$e_b1_wb$37169(); bool L_$e_id_ex$37195(); bool L_$e_ex_bf$37199(); ! bool L_$e_b0_bf$37221(); ! bool L_$e_b2_b1$37222(); ! bool L_$e_id_ex$37265(); ! bool L_$e_ex_in$37268(); bool L_$e_ex_bf$37269(); ! bool L_$e_bf_wb$37288(); ! bool L_$e_bf_wb_null$37290(); ! bool L_$e_wb_in_null$37308(); bool L_$e_ex_bf$37339(); + bool L_$e_id_ex$37405(); bool L_$e_ex_bf$37409(); bool L_$e_ex_bf$37479(); ! bool L_$e_id_ex$37545(); ! bool L_$e_ex_in$37548(); bool L_$e_ex_bf$37549(); + bool L_$e_ex_bf_null$37550(); bool L_$e_bf_bf_post$37569(); ! bool L_$e_bf_post_wb$37587(); bool L_$e_ex_bf$37619(); + bool L_$e_bf_bf_post$37639(); + bool L_$e_id_ex$37685(); bool L_$e_ex_bf$37689(); bool L_$e_ex_bf$37759(); *************** *** 1884,1897 **** bool L_$e_ex_bf$37899(); bool L_$e_ex_bf$37969(); - bool L_$e_id_ex$38035(); bool L_$e_ex_bf$38039(); - bool L_$e_bf_wb$38058(); - bool L_$e_wb_in$38076(); bool L_$e_id_ex$38105(); bool L_$e_bf_wb$38128(); bool L_$e_wb_in$38146(); ! bool L_$e_id_ex$38455(); ! bool L_$e_ex_bf$38459(); ! bool L_$e_bf_wb$38478(); --- 1885,1899 ---- bool L_$e_ex_bf$37899(); bool L_$e_ex_bf$37969(); bool L_$e_ex_bf$38039(); bool L_$e_id_ex$38105(); + bool L_$e_ex_bf$38109(); bool L_$e_bf_wb$38128(); bool L_$e_wb_in$38146(); ! bool L_$e_id_ex$38175(); ! bool L_$e_bf_wb$38198(); ! bool L_$e_wb_in$38216(); ! bool L_$e_id_ex$38525(); ! bool L_$e_ex_bf$38529(); ! bool L_$e_bf_wb$38548(); *************** *** 2545,2548 **** --- 2547,2551 ---- void __dec_548(); void __dec_549(); + void __dec_550(); }; Index: more_managers.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/more_managers.hpp,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** more_managers.hpp 19 Aug 2005 03:15:05 -0000 1.4 --- more_managers.hpp 23 Aug 2005 19:47:52 -0000 1.5 *************** *** 394,397 **** --- 394,401 ---- unsigned get_current_pc(); + void set_armsim(arm_simulator *armsim) { + _armsim = armsim; + } + private: *************** *** 411,414 **** --- 415,419 ---- // two flags for debugging int branch_taken, first_inst; + arm_simulator *_armsim; }; *************** *** 460,466 **** */ void write_token(const _UINT_T(32)& val, _BASE_MACHINE *obj) { ! isRead = 1 - (val.val() & 1); ! size = (val.val()>>1)&7; ! count = val.val()>>4; trigger = true; } --- 465,472 ---- */ void write_token(const _UINT_T(32)& val, _BASE_MACHINE *obj) { ! isRead = val.val() & 2; ! isWrite = val.val() & 1; ! size = (val.val()>>2)&7; ! count = val.val()>>5; trigger = true; } *************** *** 505,509 **** unsigned addr; unsigned size; ! bool isRead; bool trigger; --- 511,515 ---- unsigned addr; unsigned size; ! bool isRead,isWrite; bool trigger; Index: more_managers.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/more_managers.cpp,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** more_managers.cpp 19 Aug 2005 03:15:05 -0000 1.3 --- more_managers.cpp 23 Aug 2005 19:47:52 -0000 1.4 *************** *** 56,60 **** #ifdef DEBUG //fprintf(stderr, "0x%08x\n", current_pc); ! fprintf(stderr, "0x%08x : 0x%08x\n", current_pc, iw); #endif } --- 56,60 ---- #ifdef DEBUG //fprintf(stderr, "0x%08x\n", current_pc); ! fprintf(stderr, "proc %d:: 0x%08x : 0x%08x\n", _armsim->get_procid(), current_pc, iw); #endif } *************** *** 80,85 **** if (status==1 && !dmcu->is_busy()) { ! if (isRead) ! dmcu->start_read(addr, &val, size); else { val = mMemWrite->get_value().val(); --- 80,91 ---- if (status==1 && !dmcu->is_busy()) { ! if (isRead) { ! if (isWrite) { // swap operation ! val = mMemWrite->get_value().val(); ! dmcu->start_swap(addr, &val, size); ! } ! else ! dmcu->start_read(addr, &val, size); ! } else { val = mMemWrite->get_value().val(); *************** *** 106,111 **** if (trigger) { trigger = false; ! _armsim->syscall_start(sc_num); ! busy = true; } else if (busy) { --- 112,147 ---- if (trigger) { trigger = false; ! ! // interpret some specially added ones ! switch (sc_num) { ! ! case 514: // get processor id ! _armsim->write_gpr(0, _armsim->get_procid()); ! break; ! case 515: // get cycle count ! { ! uint64_t c = _armsim->get_cycle_count(); ! _armsim->write_gpr(0, (uint32_t) (c)); ! _armsim->write_gpr(1, (uint32_t) (c >> 32)); ! break; ! } ! case 516: // get system cycle count ! { ! uint64_t c = _armsim->get_system_cycle_count(); ! _armsim->write_gpr(0, (uint32_t) (c)); ! _armsim->write_gpr(1, (uint32_t) (c >> 32)); ! break; ! } ! case 517: ! _armsim->set_clock_divider(_armsim->read_gpr(0)); ! break; ! case 518: ! _armsim->sleep(_armsim->read_gpr(0)); ! break; ! default: ! _armsim->syscall_start(sc_num); ! busy = true; ! break; ! } } else if (busy) { Index: cache.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/cache.h,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** cache.h 21 Aug 2005 04:23:12 -0000 1.6 --- cache.h 23 Aug 2005 19:47:52 -0000 1.7 *************** *** 69,72 **** --- 69,73 ---- } + public: *************** *** 85,93 **** /* mask for index */ ! index_mask = (n_block/n_assoc) - 1; tag_shifts = block_bits + bsize_bits - assoc_bits; tags = new block_t[n_block]; ! round_robin_index = new uint16_t[n_block/n_assoc]; } --- 86,95 ---- /* mask for index */ ! index_mask = (n_block>>assoc_bits) - 1; tag_shifts = block_bits + bsize_bits - assoc_bits; tags = new block_t[n_block]; ! round_robin_index = new uint16_t[n_block>>assoc_bits]; ! } *************** *** 99,103 **** virtual void reset() { memset(tags, 0, sizeof(block_t)*n_block); ! memset(round_robin_index, 0, sizeof(uint16_t)*n_block/n_assoc); } --- 101,105 ---- virtual void reset() { memset(tags, 0, sizeof(block_t)*n_block); ! memset(round_robin_index, 0, (sizeof(uint16_t)*n_block)>>assoc_bits); } *************** *** 106,109 **** --- 108,112 ---- virtual bool read(target_addr_t addr, unsigned size, uint32_t *val) = 0; virtual bool write(target_addr_t addr, unsigned size, uint32_t *val) = 0; + virtual bool swap(target_addr_t addr, unsigned size, uint32_t *val) = 0; /* to be called by biu for flushing, return the block of data */ *************** *** 182,194 **** } ! /* should never call write */ bool write(target_addr_t addr, unsigned size, uint32_t *val) { return false; } /* invalidate a line of cache */ bool biu_invalidate(target_addr_t addr) { tag_t *blk = look_up(addr); ! if (!blk || !blk->valid) return false; blk->valid = false; return true; --- 185,201 ---- } ! /* should never call write or swap*/ bool write(target_addr_t addr, unsigned size, uint32_t *val) { return false; } + bool swap(target_addr_t addr, unsigned size, uint32_t *val) { + return false; + } + /* invalidate a line of cache */ bool biu_invalidate(target_addr_t addr) { tag_t *blk = look_up(addr); ! if (!blk) return false; blk->valid = false; return true; *************** *** 294,299 **** /* if the channel is busy, wait */ ! if (biu->is_busy()) { ! state = PENDING_LOAD; } else { --- 301,306 ---- /* if the channel is busy, wait */ ! if (!biu->lock(this)) { ! state = PENDING_LOCK; } else { *************** *** 338,341 **** --- 345,352 ---- } + bool swap(target_addr_t addr, unsigned size, uint32_t *val) { + return false; + } + uint8_t *biu_flush(target_addr_t addr) { return NULL; *************** *** 345,350 **** bool biu_invalidate(target_addr_t addr) { tag_t *blk = look_up(addr); ! if (!blk || !blk->valid) return false; blk->valid = false; return true; } --- 356,367 ---- bool biu_invalidate(target_addr_t addr) { tag_t *blk = look_up(addr); ! if (!blk) return false; blk->valid = false; + + struct data_t *line = values + (blk - tags); + if (state!=IDLE && reqLine==line) { + if (state==WAITING_LOAD) biu->unlock(this); + state = IDLE; + } return true; } *************** *** 356,361 **** void update_on_clock() { ! if (state==PENDING_LOAD) { ! if (!biu->is_busy()) { biu->post_request(this, true, aligned_addr, bsize, reqLine->data); --- 373,378 ---- void update_on_clock() { ! if (state==PENDING_LOCK) { ! if (biu->lock(this)) { biu->post_request(this, true, aligned_addr, bsize, reqLine->data); *************** *** 366,369 **** --- 383,387 ---- reqTag->valid = true; state = IDLE; + biu->unlock(this); } } *************** *** 385,389 **** enum { IDLE, ! PENDING_LOAD, WAITING_LOAD } state; --- 403,407 ---- enum { IDLE, ! PENDING_LOCK, WAITING_LOAD } state; *************** *** 460,534 **** reqTag = look_up(addr); ! if (!reqTag) { ! ! ! nReadMisses++; - /* read the block in */ - reqTag = allocate_block(addr); reqLine = values + (reqTag - tags); ! aligned_addr = addr>>bsize_bits << bsize_bits; ! ! // need to flush this line ! if (reqTag->valid && reqLine->dirty) { ! // get the address of the line ! target_addr_t flush_index = (reqTag-tags)/n_assoc; ! flush_addr = get_address(flush_index, reqTag->tag); ! // if the channel is busy, wait */ ! if (biu->is_busy()) { ! state = PENDING_FLUSH; ! } ! else { ! biu->post_request(this, false, ! flush_addr, bsize, reqLine->data); ! state = WAITING_FLUSH; ! } ! } ! else { ! reqLine->dirty = false; ! // if the channel is busy, wait */ ! if (biu->is_busy()) { ! state = PENDING_LOAD; ! } ! else { ! biu->post_request(this, true, ! aligned_addr, bsize, reqLine->data); ! state = WAITING_LOAD; ! } ! } ! reqTag->tag = get_tag(addr); return false; } - reqLine = values + (reqTag - tags); - uint8_t *ptr = reqLine->data + (addr&(bsize-1)); - - if (size==4) - #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN - *val = swap_word(*reinterpret_cast<uint32_t *>(ptr)); - #else - *val = *reinterpret_cast<uint32_t *>(ptr); - #endif - else if (size==1) - *val = *ptr; - else if (size==2) - #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN - *val = swap_half_word(*reinterpret_cast<uint16_t *>(ptr)); - #else - *val = *reinterpret_cast<uint16_t *>(ptr); - #endif - else { - fprintf(stderr, "%s: illegal access size, must be 1, 2 or 4 - " - "addr=%08x size=%d\n", name.c_str(), addr, size); - exit(1); - } - - nReads++; - return true; } --- 478,500 ---- reqTag = look_up(addr); ! if (reqTag) { reqLine = values + (reqTag - tags); + uint8_t *ptr = reqLine->data + (addr&(bsize-1)); + read_content(ptr, addr, size, val); ! nReads++; ! return true; ! } ! else { ! nReadMisses++; ! flush_and_load(addr); return false; } } *************** *** 552,577 **** reqLine->dirty = true; // dirty line now ! uint8_t *ptr = reqLine->data + addr%bsize; ! ! /* swap the value if necessary */ ! if (size==4) ! #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! *reinterpret_cast<uint32_t *>(ptr) = swap_word(*val); ! #else ! *reinterpret_cast<uint32_t *>(ptr) = *val; ! #endif ! else if (size==1) ! *ptr = (uint8_t)(*val); ! else if (size==2) ! #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN ! *reinterpret_cast<uint16_t *>(ptr) = ! swap_half_word((uint16_t)*val); ! #else ! *reinterpret_cast<uint16_t *>(ptr) = (uint16_t)*val; ! #endif ! else ! fprintf(stderr, "%s: illegal access size, must be 1, 2 or 4 - " ! "addr=%08x size=%d\n", name.c_str(), addr, size); nWrites++; --- 518,524 ---- reqLine->dirty = true; // dirty line now ! uint8_t *ptr = reqLine->data + (addr&(bsize-1)); + write_content(ptr, addr, size, val); nWrites++; *************** *** 586,626 **** nWriteMisses++; ! // remember the address ! aligned_addr = addr>>bsize_bits<<bsize_bits; - /* locate a block */ - reqTag = allocate_block(addr); reqLine = values + (reqTag - tags); ! // need to flush this line ! if (reqTag->valid && reqLine->dirty) { ! // get the address of the line ! target_addr_t flush_index = (reqTag-tags)/n_assoc; ! flush_addr = get_address(flush_index, reqTag->tag); ! // wait for biu ! if (biu->is_busy()) { ! state = PENDING_FLUSH; ! } ! else { ! biu->post_request(this, ! false, flush_addr, bsize, reqLine->data); ! state = WAITING_FLUSH; ! } ! } ! else { // need to load the line ! reqLine->dirty = false; ! if (biu->is_busy()) { ! state = PENDING_LOAD; ! } ! else { ! biu->post_request(this, ! true, aligned_addr, bsize, reqLine->data); ! state = WAITING_LOAD; ! } } ! reqTag->tag = get_tag(addr); return false; --- 533,585 ---- nWriteMisses++; ! flush_and_load(addr); ! ! return false; ! } ! } ! ! bool swap(target_addr_t addr, unsigned size, uint32_t *val) { ! ! /* if cache busy, cannot do anything */ ! if (state!=IDLE) return false; ! ! /* check that this is not across cache line boundary */ ! if ((addr>>bsize_bits)!=((addr+size-1)>>bsize_bits)) { ! fprintf(stderr, "%s: illegal access crosses line boundary - " ! "addr=%08x size=%d\n", name.c_str(), addr, size); ! exit(1); ! } ! ! /* if in cache, then update the cache line with data */ ! reqTag = look_up(addr); ! if (reqTag) { reqLine = values + (reqTag - tags); ! uint8_t *ptr = reqLine->data + addr%bsize; ! uint32_t rval; ! read_content(ptr, addr, size, &rval); ! write_content(ptr, addr, size, val); ! nWrites++; ! nReads++; ! ! /* notify the write so that others can invalidate their stale data ! in a SMP configuration */ ! if (rval!=*val) {// do not notify too frequently for spin locks ! biu->notify_write(this, addr); ! reqLine->dirty = true; // dirty line now } ! *val = rval; ! return true; ! } ! else { ! ! nWriteMisses++; ! nReadMisses++; ! ! flush_and_load(addr); return false; *************** *** 636,641 **** // if pending to flush this line, can skip waiting ! if (state==PENDING_FLUSH && reqLine==line) { ! state = PENDING_LOAD; } --- 595,602 ---- // if pending to flush this line, can skip waiting ! // since this only happens when another cache is loading this line, ! // this cache cannot be holding the biu lock ! if (state==PENDING_LOCK_FLUSH && reqLine==line) { ! state = PENDING_LOCK_LOAD; } *************** *** 651,662 **** bool biu_invalidate(target_addr_t addr) { ! tag_t *blk = look_up(addr); ! if (!blk || !blk->valid) return false; ! struct data_t *line = values + (blk - tags); ! // this state should not occur ! assert (!(state==PENDING_FLUSH && reqLine==line)); ! blk->valid = false; return true; } --- 612,631 ---- bool biu_invalidate(target_addr_t addr) { ! tag_t *tag = look_up(addr); ! if (!tag) { ! return false; ! } ! tag->valid = false; ! ! // if loading this line, abort action ! struct data_t *line = values + (tag - tags); ! if (state!=IDLE && reqLine==line) { ! if (state==WAITING_FLUSH || state==WAITING_LOAD) ! biu->unlock(this); ! state = IDLE; ! } ! return true; } *************** *** 666,670 **** if (tag) { struct data_t *line = values + (tag - tags); ! return line ->dirty; } return false; --- 635,639 ---- if (tag) { struct data_t *line = values + (tag - tags); ! return line->dirty; } return false; *************** *** 675,680 **** switch (state) { ! case PENDING_FLUSH: ! if (!biu->is_busy()) { biu->post_request(this, false, flush_addr, bsize, reqLine->data); --- 644,650 ---- switch (state) { ! case PENDING_LOCK_FLUSH: ! if (biu->lock(this)) { ! reqLine->dirty = false; biu->post_request(this, false, flush_addr, bsize, reqLine->data); *************** *** 685,695 **** case WAITING_FLUSH: if (biu->get_ack(this)) { ! reqLine->dirty = false; ! state = PENDING_LOAD; } // fall through here ! case PENDING_LOAD: ! if (!biu->is_busy()) { biu->post_request(this, true, aligned_addr, bsize, reqLine->data); --- 655,673 ---- case WAITING_FLUSH: if (biu->get_ack(this)) { ! reqTag->valid = true; ! reqTag->tag = get_tag(aligned_addr); ! biu->post_request(this, true, ! aligned_addr, bsize, reqLine->data); ! state = WAITING_LOAD; } + break; // fall through here ! case PENDING_LOCK_LOAD: ! if (biu->lock(this)) { ! // make valid bit true once starting to load ! // so that it can be invalidated if other modifies the line ! reqTag->valid = true; ! reqTag->tag = get_tag(aligned_addr); biu->post_request(this, true, aligned_addr, bsize, reqLine->data); *************** *** 701,705 **** if (biu->get_ack(this)) { state = IDLE; ! reqTag->valid = true; } break; --- 679,683 ---- if (biu->get_ack(this)) { state = IDLE; ! biu->unlock(this); } break; *************** *** 732,739 **** enum { IDLE, ! PENDING_FLUSH, ! WAITING_FLUSH, ! PENDING_LOAD, ! WAITING_LOAD } state; --- 710,717 ---- enum { IDLE, ! PENDING_LOCK_FLUSH, // waiting for lock to flush ! WAITING_FLUSH, // waiting for flush to finish ! PENDING_LOCK_LOAD, // waiting for lock to load ! WAITING_LOAD // waiting for load to finish } state; *************** *** 744,747 **** --- 722,823 ---- struct data_t *reqLine; struct data_t *values; //[n_block/n_assoc][n_assoc]; + + + private: + + void read_content(uint8_t *ptr, target_addr_t addr, + unsigned size, uint32_t *val) { + + if (size==4) + #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN + *val = swap_word(*reinterpret_cast<uint32_t *>(ptr)); + #else + *val = *reinterpret_cast<uint32_t *>(ptr); + #endif + else if (size==1) + *val = *ptr; + else if (size==2) + #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN + *val = swap_half_word(*reinterpret_cast<uint16_t *>(ptr)); + #else + *val = *reinterpret_cast<uint16_t *>(ptr); + #endif + else { + fprintf(stderr, "%s: illegal access size, must be 1, 2 or 4 - " + "addr=%08x size=%d\n", name.c_str(), addr, size); + exit(1); + } + } + + void write_content(uint8_t *ptr, target_addr_t addr, + unsigned size, uint32_t *val) { + + /* swap the value if necessary */ + if (size==4) + #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN + *reinterpret_cast<uint32_t *>(ptr) = swap_word(*val); + #else + *reinterpret_cast<uint32_t *>(ptr) = *val; + #endif + else if (size==1) + *ptr = (uint8_t)(*val); + else if (size==2) + #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN + *reinterpret_cast<uint16_t *>(ptr) = + swap_half_word((uint16_t)*val); + #else + *reinterpret_cast<uint16_t *>(ptr) = (uint16_t)*val; + #endif + else + fprintf(stderr, "%s: illegal access size, must be 1, 2 or 4 - " + "addr=%08x size=%d\n", name.c_str(), addr, size); + } + + + void flush_and_load(target_addr_t addr) { + + /* read the block in */ + reqTag = allocate_block(addr); + reqLine = values + (reqTag - tags); + + aligned_addr = addr>>bsize_bits << bsize_bits; + + // need to flush this line + if (reqTag->valid && reqLine->dirty) { + + // get the address of the line + target_addr_t flush_index = (reqTag-tags)>>assoc_bits; + flush_addr = get_address(flush_index, reqTag->tag); + + // if the channel is busy, wait */ + if (!biu->lock(this)) { + state = PENDING_LOCK_FLUSH; + } + else { + reqTag->valid = false; + biu->post_request(this, false, + flush_addr, bsize, reqLine->data); + state = WAITING_FLUSH; + } + } + else { + reqTag->valid = false; + // if the channel is busy, wait */ + if (!biu->lock(this)) { + state = PENDING_LOCK_LOAD; + } + else { + // make valid bit true once starting to load + // so that it can be invalidated if other modifies the line + reqTag->valid = true; + reqTag->tag = get_tag(aligned_addr); + biu->post_request(this, true, + aligned_addr, bsize, reqLine->data); + state = WAITING_LOAD; + } + } + + } + }; Index: armsim.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.cpp,v retrieving revision 1.7 retrieving revision 1.8 diff -C2 -d -r1.7 -r1.8 *** armsim.cpp 21 Aug 2005 04:23:12 -0000 1.7 --- armsim.cpp 23 Aug 2005 19:47:52 -0000 1.8 *************** *** 66,69 **** --- 66,70 ---- mNewPC->connect(mRF); mSC->set_armsim(this); + mIF->set_armsim(this); mCoProc->set_armsim(this); *************** *** 79,82 **** --- 80,86 ---- syscall_buf = NULL; + + c_div = 1; + c_count = 0; /* reset every thing */ *************** *** 152,155 **** --- 156,161 ---- work_it = work_list.erase(work_it); } + + c_count = 0; } *************** *** 228,231 **** --- 234,239 ---- #endif + if (c_count==0) { + /** Activate all OSMs in order. */ for (work_it=work_list.begin(); work_it!=work_list.end();) { *************** *** 272,280 **** mSC->update_on_clock(); - imcu->update_on_clock(); - dmcu->update_on_clock(); - biu->update_on_clock(); - syscall_update(); } --- 280,297 ---- mSC->update_on_clock(); syscall_update(); + + c_count = c_div; + } + + c_count--; + system_cycle_count++; + + // memory operates at normal speed otherwise bus will be clogged + imcu->update_on_clock(); + dmcu->update_on_clock(); + + if (use_self_mem) biu->update_on_clock(); + } *************** *** 440,441 **** --- 457,470 ---- } + + void arm_simulator::clone_states(arm_simulator *sim) + { + for (unsigned ii=0; ii<16; ii++) + write_gpr(ii, sim->read_gpr(ii)); + + write_cpsr(sim->read_cpsr()); + + /* set brk point for syscall interpretation. */ + syscall_set_brk(sim->syscall_get_brk()); + syscall_set_mmap_brk(sim->syscall_get_mmap_brk()); + } Index: Makefile.am =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/Makefile.am,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** Makefile.am 21 Aug 2005 04:23:12 -0000 1.5 --- Makefile.am 23 Aug 2005 19:47:52 -0000 1.6 *************** *** 20,24 **** libarmsim_a_SOURCES = define.cpp machines.cpp \ ! main.cpp armsim.cpp more_managers.cpp \ ext_func.cpp fetch_oper_dec.cpp biu.cpp \ mang_list.hpp armsim.hpp \ --- 20,24 ---- libarmsim_a_SOURCES = define.cpp machines.cpp \ ! armsim.cpp more_managers.cpp \ ext_func.cpp fetch_oper_dec.cpp biu.cpp \ mang_list.hpp armsim.hpp \ Index: fetch_oper_pat.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/fetch_oper_pat.hpp,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** fetch_oper_pat.hpp 19 Aug 2005 03:15:05 -0000 1.5 --- fetch_oper_pat.hpp 23 Aug 2005 19:47:52 -0000 1.6 *************** *** 3,19 **** Input statistics ! Total entries : 1284 ! Unique labels : 550 ! Shannon entropy : 9.10075 ! Huffman tree height : 9.13662 Decoder characteristics Gamma : 0.25 1 bit only : 0 [...3476 lines suppressed...] ! _FUNC_CALL(DEC_fetch_oper_unknown); } } --- 5304,5319 ---- _STUB_ENTRY(stub_0_20) { ! if _PATTERN_TRUE(0x00000f60, 0x00000000) { ! if _PATTERN_TRUE(0x00000090, 0x00000090) { ! _FUNC_CALL(DEC_fetch_oper_swapb_); ! } else { ! _FUNC_CALL(DEC_fetch_oper_unknown); ! } } else { ! if _PATTERN_TRUE(0x00000090, 0x00000090) { ! _FUNC_CALL(DEC_fetch_oper_store_ext_imm_mem_mode_6_); ! } else { ! _FUNC_CALL(DEC_fetch_oper_unknown); ! } } } Index: main.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/main.cpp,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** main.cpp 21 Aug 2005 04:23:12 -0000 1.6 --- main.cpp 23 Aug 2005 19:47:52 -0000 1.7 *************** *** 93,99 **** if(prog_name) { ! memory *mem = new memory(); ! bus_interface *biu = ! new bus_interface("biu", mem, n_mem_rlat, n_mem_wlat); sima = new arm_simulator(verbose, need_fpe, true, --- 93,99 ---- if(prog_name) { ! // memory *mem = new memory(); ! // bus_interface *biu = ! // new bus_interface("biu", mem, n_mem_rlat, n_mem_wlat); sima = new arm_simulator(verbose, need_fpe, true, *************** *** 102,106 **** n_itlb_blk, n_itlb_assoc, n_itlb_psize, n_dtlb_blk, n_dtlb_assoc, n_dtlb_psize, n_tlb_lat, ! mem, biu); signal(SIGUSR1, sig_handler); --- 102,106 ---- n_itlb_blk, n_itlb_assoc, n_itlb_psize, n_dtlb_blk, n_dtlb_assoc, n_dtlb_psize, n_tlb_lat, ! NULL, NULL); signal(SIGUSR1, sig_handler); *************** *** 120,123 **** --- 120,124 ---- #endif + sima->set_procid(0); sima->run(max_cnum); *************** *** 143,148 **** delete sima; ! delete biu; ! delete mem; } else usage(argv[0]); --- 144,149 ---- delete sima; ! // delete biu; ! // delete mem; } else usage(argv[0]); Index: machines.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/machines.cpp,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** machines.cpp 19 Aug 2005 03:15:05 -0000 1.6 --- machines.cpp 23 Aug 2005 19:47:52 -0000 1.7 *************** *** 70,73 **** --- 70,74 ---- #define V_store_ext_reg_m_size C_12 #define V_swap_coding C_3 + #define V_swapb_coding C_3 #define V_ldm_syn C_14 #define V_ldm_coding C_6 *************** *** 5277,5281 **** [...6361 lines suppressed...] &__act_L_$S_ID$38430, ! &__act_L_$S_EX$38431, ! &__act_L_$S_BF$38433, }; --- 46625,46638 ---- &__act_L_$S_WB$38100, &__act_L_$S_ID$38150, + &__act_L_$S_EX$38151, + &__act_L_$S_BF$38153, + &__act_L_$S_WB$38170, &__act_L_$S_ID$38220, &__act_L_$S_ID$38290, &__act_L_$S_ID$38360, &__act_L_$S_ID$38430, ! &__act_L_$S_ID$38500, ! &__act_L_$S_EX$38501, ! &__act_L_$S_BF$38503, }; Index: armsim.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.hpp,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** armsim.hpp 21 Aug 2005 04:23:12 -0000 1.5 --- armsim.hpp 23 Aug 2005 19:47:52 -0000 1.6 *************** *** 128,131 **** --- 128,132 ---- /* get the number of cycles */ uint64_t get_cycle_count() const {return cycle_count;} + uint64_t get_system_cycle_count() const {return system_cycle_count;} *************** *** 217,220 **** --- 218,237 ---- unsigned syscall_mem_size; + /* a few routines for smp support */ + + // initialize registers + void clone_states(arm_simulator *); + + // clock divider + void set_clock_divider(unsigned c) {c_div=c_count=c;} + + // sleep for c cycles + void sleep(unsigned c) {c_count=c_div+c;} + + // get the id of the processor + void set_procid(unsigned id) {procid = id;} + unsigned get_procid() const {return procid;} + + private: /* context for system call interpretation */ *************** *** 243,246 **** --- 260,264 ---- bool emu_syscall; + /* create biu and mem myself? */ bool use_self_mem; *************** *** 250,254 **** enum status_t status; ! uint64_t cycle_count; /* number of simulation cycles*/ std::list<_opt_machine_ *> work_list; --- 268,275 ---- enum status_t status; ! unsigned procid; ! uint64_t cycle_count; /* number of simulation cycles, divided*/ ! uint64_t system_cycle_count;/* number of undivided cycles */ ! unsigned c_div, c_count; std::list<_opt_machine_ *> work_list; Index: mcu.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/mcu.hpp,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** mcu.hpp 19 Aug 2005 03:15:05 -0000 1.1 --- mcu.hpp 23 Aug 2005 19:47:52 -0000 1.2 *************** *** 37,41 **** assert(state==IDLE); ! buf_read = true; buf_val_ptr = val; buf_size = size; --- 37,41 ---- assert(state==IDLE); ! buf_mode = MCU_READ; buf_val_ptr = val; buf_size = size; *************** *** 51,55 **** assert(state==IDLE); ! buf_read = false; buf_val_ptr = val; buf_size = size; --- 51,55 ---- assert(state==IDLE); ! buf_mode = MCU_WRITE; buf_val_ptr = val; buf_size = size; *************** *** 61,64 **** --- 61,78 ---- } + void start_swap(target_addr_t addr, uint32_t *val, unsigned size) { + + assert(state==IDLE); + + buf_mode = MCU_SWAP; + buf_val_ptr = val; + buf_size = size; + buf_addr = addr; + buf_blk_ptr = NULL; + + state = WAITING_TLB; + update(); + } + // Read an array of bytes from memory void start_read_block(target_addr_t addr, uint8_t *ptr, unsigned size) { *************** *** 67,71 **** assert(ptr); ! buf_read = true; buf_size = size; buf_addr = addr; --- 81,85 ---- assert(ptr); ! buf_mode = MCU_READ; buf_size = size; buf_addr = addr; *************** *** 81,85 **** assert(ptr); ! buf_read = false; buf_size = size; buf_addr = addr; --- 95,99 ---- assert(ptr); ! buf_mode = MCU_WRITE; buf_size = size; buf_addr = addr; *************** *** 112,117 **** if (buf_blk_ptr==NULL) { ! if (buf_read && cash->read(buf_addr, buf_size, buf_val_ptr) || ! !buf_read && cash->write(buf_addr, buf_size, buf_val_ptr)) state = IDLE; } --- 126,135 ---- if (buf_blk_ptr==NULL) { ! if (buf_mode==MCU_READ && ! cash->read(buf_addr, buf_size, buf_val_ptr) || ! buf_mode==MCU_WRITE && ! cash->write(buf_addr, buf_size, buf_val_ptr) || ! buf_mode==MCU_SWAP && ! cash->swap(buf_addr, buf_size, buf_val_ptr)) state = IDLE; } *************** *** 120,124 **** uint32_t val; ! if (buf_read && cash->read(buf_addr, 1, &val)) { *buf_blk_ptr = (uint8_t)val; buf_blk_ptr++; --- 138,142 ---- uint32_t val; ! if (buf_mode==MCU_READ && cash->read(buf_addr, 1, &val)) { *buf_blk_ptr = (uint8_t)val; buf_blk_ptr++; *************** *** 126,130 **** buf_size--; } ! else if (!buf_read) { val = *buf_blk_ptr; --- 144,148 ---- buf_size--; } ! else if (buf_mode==MCU_WRITE) { val = *buf_blk_ptr; *************** *** 153,157 **** /* buffered request information */ ! bool buf_read; // is read? uint32_t *buf_val_ptr; unsigned buf_size; --- 171,180 ---- /* buffered request information */ ! enum { ! MCU_READ, ! MCU_WRITE, ! MCU_SWAP ! } buf_mode; // is read? ! uint32_t *buf_val_ptr; unsigned buf_size; Index: fetch_oper_tab.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/fetch_oper_tab.hpp,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** fetch_oper_tab.hpp 19 Aug 2005 03:15:05 -0000 1.3 --- fetch_oper_tab.hpp 23 Aug 2005 19:47:52 -0000 1.4 *************** *** 3691,3699 **** } unsigned DEC_fetch_oper_ldm_update_rn_(_INST_T inst) { #ifdef _DUMP_DECODE std::cerr << "ldm_update_rn_" << std::endl; #endif ! return 527; } --- 3691,3706 ---- } + unsigned DEC_fetch_oper_swapb_(_INST_T inst) { + #ifdef _DUMP_DECODE + std::cerr << "swapb_" << std::endl; + #endif + return 527; + } + unsigned DEC_fetch_oper_ldm_update_rn_(_INST_T inst) { #ifdef _DUMP_DECODE std::cerr << "ldm_update_rn_" << std::endl; #endif ! return 528; } *************** *** 3702,3706 **** std::cerr << "ldm_noupdate_rn_" << std::endl; #endif ! return 528; } --- 3709,3713 ---- std::cerr << "ldm_noupdate_rn_" << std::endl; #endif ! return 529; } *************** *** 3709,3713 **** std::cerr << "stm_update_rn_" << std::endl; #endif ! return 529; } --- 3716,3720 ---- std::cerr << "stm_update_rn_" << std::endl; #endif ! return 530; } *************** *** 3716,3720 **** std::cerr << "stm_noupdate_rn_" << std::endl; #endif ! return 530; } --- 3723,3727 ---- std::cerr << "stm_noupdate_rn_" << std::endl; #endif ! return 531; } *************** *** 3723,3727 **** std::cerr << "mult_mla_" << std::endl; #endif ! return 531; } --- 3730,3734 ---- std::cerr << "mult_mla_" << std::endl; #endif ! return 532; } *************** *** 3730,3734 **** std::cerr << "mult_mlas_" << std::endl; #endif ! return 532; } --- 3737,3741 ---- std::cerr << "mult_mlas_" << std::endl; #endif ! return 533; } *************** *** 3737,3741 **** std::cerr << "mult_mul_" << std::endl; #endif ! return 533; } --- 3744,3748 ---- std::cerr << "mult_mul_" << std::endl; #endif ! return 534; } *************** *** 3744,3748 **** std::cerr << "mult_muls_" << std::endl; #endif ! return 534; } --- 3751,3755 ---- std::cerr << "mult_muls_" << std::endl; #endif ! return 535; } *************** *** 3751,3755 **** std::cerr << "mult_long_smull_" << std::endl; #endif ! return 535; } --- 3758,3762 ---- std::cerr << "mult_long_smull_" << std::endl; #endif ! return 536; } *************** *** 3758,3762 **** std::cerr << "mult_long_smulls_" << std::endl; #endif ! return 536; } --- 3765,3769 ---- std::cerr << "mult_long_smulls_" << std::endl; #endif ! return 537; } *************** *** 3765,3769 **** std::cerr << "mult_long_smlal_" << std::endl; #endif ! return 537; } --- 3772,3776 ---- std::cerr << "mult_long_smlal_" << std::endl; #endif ! return 538; } *************** *** 3772,3776 **** std::cerr << "mult_long_smlals_" << std::endl; #endif ! return 538; } --- 3779,3783 ---- std::cerr << "mult_long_smlals_" << std::endl; #endif ! return 539; } *************** *** 3779,3783 **** std::cerr << "mult_long_umull_" << std::endl; #endif ! return 539; } --- 3786,3790 ---- std::cerr << "mult_long_umull_" << std::endl; #endif ! return 540; } *************** *** 3786,3790 **** std::cerr << "mult_long_umulls_" << std::endl; #endif ! return 540; } --- 3793,3797 ---- std::cerr << "mult_long_umulls_" << std::endl; #endif ! return 541; } *************** *** 3793,3797 **** std::cerr << "mult_long_umlal_" << std::endl; #endif ! return 541; } --- 3800,3804 ---- std::cerr << "mult_long_umlal_" << std::endl; #endif ! return 542; } *************** *** 3800,3804 **** std::cerr << "mult_long_umlals_" << std::endl; #endif ! return 542; } --- 3807,3811 ---- std::cerr << "mult_long_umlals_" << std::endl; #endif ! return 543; } *************** *** 3807,3811 **** std::cerr << "syscall_" << std::endl; #endif ! return 543; } --- 3814,3818 ---- std::cerr << "syscall_" << std::endl; #endif ! return 544; } *************** *** 3814,3818 **** std::cerr << "coproc_inst_cdp_" << std::endl; #endif ! return 544; } --- 3821,3825 ---- std::cerr << "coproc_inst_cdp_" << std::endl; #endif ! return 545; } *************** *** 3821,3825 **** std::cerr << "coproc_inst_mcr_" << std::endl; #endif ! return 545; } --- 3828,3832 ---- std::cerr << "coproc_inst_mcr_" << std::endl; #endif ! return 546; } *************** *** 3828,3832 **** std::cerr << "coproc_inst_mrc_" << std::endl; #endif ! return 546; } --- 3835,3839 ---- std::cerr << "coproc_inst_mrc_" << std::endl; #endif ! return 547; } *************** *** 3835,3839 **** std::cerr << "coproc_inst_ldc_" << std::endl; #endif ! return 547; } --- 3842,3846 ---- std::cerr << "coproc_inst_ldc_" << std::endl; #endif ! return 548; } *************** *** 3842,3846 **** std::cerr << "coproc_inst_stc_" << std::endl; #endif ! return 548; } --- 3849,3853 ---- std::cerr << "coproc_inst_stc_" << std::endl; #endif ! return 549; } *************** *** 3849,3853 **** std::cerr << "unknown" << std::endl; #endif ! return 549; } --- 3856,3860 ---- std::cerr << "unknown" << std::endl; #endif ! return 550; } Index: biu.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/biu.cpp,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** biu.cpp 21 Aug 2005 04:23:12 -0000 1.1 --- biu.cpp 23 Aug 2005 19:47:52 -0000 1.2 *************** *** 13,17 **** vector<cache *>::iterator cit; for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) { ! if ((*cit)->is_block_dirty(addr)) { uint8_t *pval = (*cit)->biu_flush(addr); if (pval) { // flush occurs --- 13,17 ---- vector<cache *>::iterator cit; for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) { ! if (*cit!=cash && (*cit)->is_block_dirty(addr)) { uint8_t *pval = (*cit)->biu_flush(addr); if (pval) { // flush occurs *************** *** 31,35 **** vector<cache *>::iterator cit; for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) { ! (*cit)->biu_invalidate(addr); } } --- 31,35 ---- vector<cache *>::iterator cit; for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) { ! if (*cit!=cash) (*cit)->biu_invalidate(addr); } } --- NEW FILE: biu.h --- #ifndef __BUI_H__ #define __BUI_H__ #include <cstdio> #include <string> #include "misc.h" #include <vector> #include <cassert> namespace simulator { class cache; class bus_interface { public: bus_interface(const std::string& name, emulator::memory *mem, unsigned r_latency, unsigned w_latency, bool smp=false) : name(name), mem(mem), read_latency(r_latency), write_latency(w_latency), smp(smp) { assert(read_latency>0); assert(write_latency>0); reset(); } void reset() { naccess=nbusy=nfree=0; ack = false; delay = 0; owner = NULL; } void post_request(cache *cash, bool read, target_addr_t addr, unsigned size, void *ptr) { assert(owner==cash); naccess++; delay = read?read_latency:write_latency; ack = false; if (smp && read) { // if a read, need to check if data dirty in some cache // if a write, do nothing special smp_service_read(cash, addr, size, ptr); } else { if (read) mem->read_block(ptr, addr, size); else mem->write_block(addr, ptr, size); } return; } // get acknowledgement and clears ack bit bool get_ack(cache *cash) { assert(cash==owner); bool oldack = ack; ack = false; return oldack; } bool lock(cache *cash) { // if free then good if (owner==NULL) { owner = cash; return true; } return false; } void unlock(cache *cash) { assert(owner==cash); owner = NULL; } void update_on_clock() { if (delay>0) { if (delay==1) ack = true; --delay; nbusy++; } else { nfree++; } } void print_stats(FILE *fp) { fprintf(fp, "Total %s accesses: ", name.c_str()); dump_int64(naccess, fp); fprintf(fp, "\n%s activity: %.3f%%\n", name.c_str(), 100.0*nbusy/(nbusy+nfree)); } void notify_write(cache *c, target_addr_t addr) { if (smp) { smp_service_write(c, addr); } return; } void register_icache(cache *c) { icaches.push_back(c); } void register_dcache(cache *c) { dcaches.push_back(c); } private: const std::string name; const unsigned read_latency; const unsigned write_latency; const bool smp; // smp support emulator::memory *mem; uint64_t naccess; uint64_t nbusy; /*busy cycles*/ uint64_t nfree; /*free cycles*/ bool ack; uint32_t delay; cache *owner; std::vector<cache *> icaches; std::vector<cache *> dcaches; void smp_service_read(cache *, target_addr_t, unsigned, void *); void smp_service_write(cache *, target_addr_t); }; } #endif |
|
From: Wei Q. <wei...@us...> - 2005-08-21 04:23:20
|
Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv6307 Modified Files: Makefile.am armsim.cpp armsim.hpp cache.h checker.cpp main.cpp Added Files: biu.cpp Removed Files: BIU.h Log Message: readies for smp Index: main.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/main.cpp,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** main.cpp 19 Aug 2005 03:15:05 -0000 1.5 --- main.cpp 21 Aug 2005 04:23:12 -0000 1.6 *************** *** 11,14 **** --- 11,15 ---- #endif + using emulator::memory; using namespace simulator; *************** *** 55,58 **** --- 56,79 ---- void (*prev_sig_handler)(int); + /* subsystem memory parameters */ + int n_mem_rlat = memoryReadLatency; // latency to load a cache block + int n_mem_wlat = memoryWriteLatency; // latency to write a cache block + int n_tlb_lat = tlbLoadLatency; // latency to serve a tlb miss + + int n_itlb_blk = nITLBBlocks; // # blocks in itlb + int n_itlb_assoc = nITLBAssoc; // # associativity of icache + int n_itlb_psize = IPageSize; // # bytes in a i-page + int n_dtlb_blk = nDTLBBlocks; // # blocks in dtlb + int n_dtlb_assoc = nDTLBAssoc; // # associativity of dcache + int n_dtlb_psize = DPageSize; // # bytes in a d-page + + int n_ic_blk = nICacheBlocks; // # blocks in icache + int n_ic_assoc = nICacheAssoc; // # associativity of icache + int n_ic_bsize = ICacheLineSize; // # bytes in a icache block + int n_dc_blk = nICacheBlocks; // # blocks in dcache + int n_dc_assoc = nICacheAssoc; // # associativity of dcache + int n_dc_bsize = ICacheLineSize; // # bytes in a dcache block + + for(i = 1; i < argc; i++) { *************** *** 66,70 **** prog_name = argv[i]; break; ! } } --- 87,91 ---- prog_name = argv[i]; break; ! } } *************** *** 72,76 **** if(prog_name) { ! sima = new arm_simulator(verbose, need_fpe, true); signal(SIGUSR1, sig_handler); --- 93,106 ---- if(prog_name) { ! memory *mem = new memory(); ! bus_interface *biu = ! new bus_interface("biu", mem, n_mem_rlat, n_mem_wlat); ! ! sima = new arm_simulator(verbose, need_fpe, true, ! n_ic_blk, n_ic_assoc, n_ic_bsize, ! n_dc_blk, n_dc_assoc, n_dc_bsize, ! n_itlb_blk, n_itlb_assoc, n_itlb_psize, ! n_dtlb_blk, n_dtlb_assoc, n_dtlb_psize, n_tlb_lat, ! mem, biu); signal(SIGUSR1, sig_handler); *************** *** 113,116 **** --- 143,148 ---- delete sima; + delete biu; + delete mem; } else usage(argv[0]); Index: cache.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/cache.h,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** cache.h 19 Aug 2005 03:15:05 -0000 1.5 --- cache.h 21 Aug 2005 04:23:12 -0000 1.6 *************** *** 5,9 **** #include <string> #include "misc.h" ! #include "BIU.h" namespace simulator { --- 5,9 ---- #include <string> #include "misc.h" ! #include "biu.h" namespace simulator { *************** *** 102,112 **** } - /* invalidate a line of cache */ - bool invalidate(target_addr_t addr) { - struct block_t *blk = look_up(addr); - if (!blk || !blk->valid) return false; - blk->valid = false; - return true; - } /* data access interfaces */ --- 102,105 ---- *************** *** 114,117 **** --- 107,115 ---- virtual bool write(target_addr_t addr, unsigned size, uint32_t *val) = 0; + /* to be called by biu for flushing, return the block of data */ + virtual uint8_t *biu_flush(target_addr_t addr) = 0; + virtual bool biu_invalidate(target_addr_t addr) = 0; + virtual bool is_block_dirty(target_addr_t addr) = 0; + virtual void update_on_clock() = 0; *************** *** 189,192 **** --- 187,206 ---- } + /* invalidate a line of cache */ + bool biu_invalidate(target_addr_t addr) { + tag_t *blk = look_up(addr); + if (!blk || !blk->valid) return false; + blk->valid = false; + return true; + } + + uint8_t *biu_flush(target_addr_t addr) { + return NULL; + } + + bool is_block_dirty(target_addr_t addr) { + return false; + } + void update_on_clock() { if (delay) delay--; *************** *** 274,278 **** reqTag = allocate_block(addr); reqTag->tag = get_tag(addr); - reqTag->valid = true; reqLine = values + (reqTag - tags); --- 288,291 ---- *************** *** 285,289 **** } else { ! biu->post_request(true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } --- 298,303 ---- } else { ! biu->post_request(this, true, ! aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } *************** *** 324,336 **** } void update_on_clock() { if (state==PENDING_LOAD) { if (!biu->is_busy()) { ! biu->post_request(true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } } ! else if (state==WAITING_LOAD && biu->get_ack()) { state = IDLE; } --- 338,368 ---- } + uint8_t *biu_flush(target_addr_t addr) { + return NULL; + } + + /* invalidate a line of cache */ + bool biu_invalidate(target_addr_t addr) { + tag_t *blk = look_up(addr); + if (!blk || !blk->valid) return false; + blk->valid = false; + return true; + } + + bool is_block_dirty(target_addr_t addr) { + return false; + } + void update_on_clock() { if (state==PENDING_LOAD) { if (!biu->is_busy()) { ! biu->post_request(this, true, ! aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } } ! else if (state==WAITING_LOAD && biu->get_ack(this)) { ! reqTag->valid = true; state = IDLE; } *************** *** 409,413 **** state = IDLE; - flush_only = false; nReads = 0; --- 441,444 ---- *************** *** 446,450 **** target_addr_t flush_index = (reqTag-tags)/n_assoc; flush_addr = get_address(flush_index, reqTag->tag); - flush_only = false; // if the channel is busy, wait */ --- 477,480 ---- *************** *** 453,457 **** } else { ! biu->post_request(false, flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } --- 483,488 ---- } else { ! biu->post_request(this, false, ! flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } *************** *** 464,468 **** } else { ! biu->post_request(true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } --- 495,500 ---- } else { ! biu->post_request(this, true, ! aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } *************** *** 470,474 **** reqTag->tag = get_tag(addr); - reqTag->valid = true; return false; --- 502,505 ---- *************** *** 544,547 **** --- 575,583 ---- nWrites++; + + /* notify the write so that others can invalidate their stale data + in a SMP configuration */ + biu->notify_write(this, addr); + return true; } *************** *** 563,567 **** target_addr_t flush_index = (reqTag-tags)/n_assoc; flush_addr = get_address(flush_index, reqTag->tag); - flush_only = false; // wait for biu --- 599,602 ---- *************** *** 570,574 **** } else { ! biu->post_request(false, flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } --- 605,610 ---- } else { ! biu->post_request(this, ! false, flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } *************** *** 580,584 **** } else { ! biu->post_request(true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } --- 616,621 ---- } else { ! biu->post_request(this, ! true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } *************** *** 586,590 **** reqTag->tag = get_tag(addr); - reqTag->valid = true; return false; --- 623,626 ---- *************** *** 593,623 **** /* flush the block containing addr, but does NOT invalidate */ ! bool flush_request(target_addr_t addr) { ! ! /* if cache busy, cannot do anything */ ! if (state!=IDLE) return false; ! /* if in cache, then update the cache line with data */ ! reqTag = look_up(addr); ! if (reqTag) { ! flush_addr = addr >> bsize_bits << bsize_bits; ! reqLine = values + (reqTag - tags); ! flush_only = true; ! if (reqLine->dirty) { ! // wait for biu ! if (biu->is_busy()) { ! state = PENDING_FLUSH; ! } ! else { ! biu->post_request(false, flush_addr, bsize, reqLine->data); ! state = WAITING_FLUSH; ! } } - return false; } ! else // nothing to be done ! return true; } --- 629,672 ---- /* flush the block containing addr, but does NOT invalidate */ ! uint8_t *biu_flush(target_addr_t addr) { ! tag_t *tag = look_up(addr); ! if (tag) { ! struct data_t *line = values + (tag - tags); ! // if pending to flush this line, can skip waiting ! if (state==PENDING_FLUSH && reqLine==line) { ! state = PENDING_LOAD; ! } ! if (line->dirty) { ! line->dirty = false; ! return line->data; } } ! return NULL; ! } ! ! /* invalidate a line of cache */ ! bool biu_invalidate(target_addr_t addr) { ! ! tag_t *blk = look_up(addr); ! ! if (!blk || !blk->valid) return false; ! ! struct data_t *line = values + (blk - tags); ! // this state should not occur ! assert (!(state==PENDING_FLUSH && reqLine==line)); ! blk->valid = false; ! return true; ! } ! ! bool is_block_dirty(target_addr_t addr) { ! tag_t *tag = look_up(addr); ! if (tag) { ! struct data_t *line = values + (tag - tags); ! return line ->dirty; ! } ! return false; } *************** *** 628,632 **** case PENDING_FLUSH: if (!biu->is_busy()) { ! biu->post_request(false, flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } --- 677,682 ---- case PENDING_FLUSH: if (!biu->is_busy()) { ! biu->post_request(this, ! false, flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } *************** *** 634,645 **** case WAITING_FLUSH: ! if (biu->get_ack()) { reqLine->dirty = false; ! if (flush_only) { ! state = IDLE; ! break; ! } ! else ! state = PENDING_LOAD; } // fall through here --- 684,690 ---- case WAITING_FLUSH: ! if (biu->get_ack(this)) { reqLine->dirty = false; ! state = PENDING_LOAD; } // fall through here *************** *** 647,651 **** case PENDING_LOAD: if (!biu->is_busy()) { ! biu->post_request(true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } --- 692,697 ---- case PENDING_LOAD: if (!biu->is_busy()) { ! biu->post_request(this, true, ! aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } *************** *** 653,657 **** case WAITING_LOAD: ! if (biu->get_ack()) state = IDLE; break; --- 699,706 ---- case WAITING_LOAD: ! if (biu->get_ack(this)) { ! state = IDLE; ! reqTag->valid = true; ! } break; *************** *** 692,697 **** uint64_t nWrites, nWriteMisses; - bool flush_only; - tag_t *reqTag; struct data_t *reqLine; --- 741,744 ---- Index: armsim.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.cpp,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** armsim.cpp 19 Aug 2005 03:15:05 -0000 1.6 --- armsim.cpp 21 Aug 2005 04:23:12 -0000 1.7 *************** *** 25,42 **** using std::list; ! arm_simulator::arm_simulator(bool verbose, bool need_fpe, bool emu_syscall) : ! verbose(verbose), need_fpe(need_fpe), emu_syscall(emu_syscall) { ! mem = new memory(); /* create the hardware modules */ ! biu = new BIU("biu", mem, memoryReadLatency, memoryWriteLatency); ! icache = new ICache("icache", nICacheBlocks, nICacheAssoc, ICacheLineSize, ! biu); ! dcache = new DCache("dcache", nDCacheBlocks, nDCacheAssoc, DCacheLineSize, ! biu); ! itlb = new ITLB("itlb", nITLBBlocks, nITLBAssoc, IPageSize, tlbLoadLatency); ! dtlb = new DTLB("dtlb", nDTLBBlocks, nDTLBAssoc, DPageSize, tlbLoadLatency); imcu = new mcu("imcu", itlb, icache); --- 25,56 ---- using std::list; ! arm_simulator::arm_simulator(bool verbose, bool need_fpe, bool emu_syscall, ! int n_ic_blk, int n_ic_assoc, int n_ic_bsize, ! int n_dc_blk, int n_dc_assoc, int n_dc_bsize, ! int n_itlb_blk, int n_itlb_assoc, int n_itlb_psize, ! int n_dtlb_blk, int n_dtlb_assoc, int n_dtlb_psize, int n_tlb_lat, ! memory *mem_, bus_interface *biu_) : ! verbose(verbose), need_fpe(need_fpe), emu_syscall(emu_syscall), ! mem(mem_), biu(biu_) { ! //mem = new memory(); ! use_self_mem = false; ! if (mem==NULL || biu==NULL) { ! mem = new memory(); ! biu = new bus_interface("biu", mem, ! memoryReadLatency, memoryWriteLatency); ! use_self_mem = true; ! } /* create the hardware modules */ ! //biu = new BIU("biu", mem, memoryReadLatency, memoryWriteLatency); ! icache = new ICache("icache", n_ic_blk, n_ic_assoc, n_ic_bsize, biu); ! dcache = new DCache("dcache", n_dc_blk, n_dc_assoc, n_dc_bsize, biu); ! itlb = new ITLB("itlb", n_itlb_blk, n_itlb_assoc, n_itlb_psize, n_tlb_lat); ! dtlb = new DTLB("dtlb", n_dtlb_blk, n_dtlb_assoc, n_dtlb_psize, n_tlb_lat); ! ! biu->register_icache(icache); ! biu->register_dcache(dcache); imcu = new mcu("imcu", itlb, icache); *************** *** 85,94 **** delete dev_master; ! delete biu; delete icache; delete itlb; delete dcache; delete dtlb; - delete mem; delete imcu; --- 99,111 ---- delete dev_master; ! if (use_self_mem) { ! delete biu; ! delete mem; ! } ! delete icache; delete itlb; delete dcache; delete dtlb; delete imcu; Index: Makefile.am =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/Makefile.am,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** Makefile.am 19 Aug 2005 03:15:05 -0000 1.4 --- Makefile.am 21 Aug 2005 04:23:12 -0000 1.5 *************** *** 21,30 **** libarmsim_a_SOURCES = define.cpp machines.cpp \ main.cpp armsim.cpp more_managers.cpp \ ! ext_func.cpp fetch_oper_dec.cpp \ mang_list.hpp armsim.hpp \ define.hpp include_osm.hpp \ include_temp.hpp more_managers.hpp interface.hpp \ cache.h fetch_oper_dec.hpp mach_list.hpp \ ! BIU.h machines.hpp parms.h mcu.h \ fetch_oper_pat.hpp fetch_oper_tab.hpp func.hpp \ $(top_builddir)/emulator/syscall.cpp \ --- 21,30 ---- libarmsim_a_SOURCES = define.cpp machines.cpp \ main.cpp armsim.cpp more_managers.cpp \ ! ext_func.cpp fetch_oper_dec.cpp biu.cpp \ mang_list.hpp armsim.hpp \ define.hpp include_osm.hpp \ include_temp.hpp more_managers.hpp interface.hpp \ cache.h fetch_oper_dec.hpp mach_list.hpp \ ! biu.h machines.hpp parms.h mcu.h \ fetch_oper_pat.hpp fetch_oper_tab.hpp func.hpp \ $(top_builddir)/emulator/syscall.cpp \ *************** *** 38,44 **** $(top_builddir)/emulator/external_dev_stub.o ! AM_CPPFLAGS = -DCOMPILE_SIMULATOR include_HEADERS = parms.h more_managers.hpp \ ! include_osm.hpp cache.h BIU.h armsim.hpp \ mach_list.hpp mang_list.hpp --- 38,44 ---- $(top_builddir)/emulator/external_dev_stub.o ! libarmsim_a_CPPFLAGS = -DCOMPILE_SIMULATOR include_HEADERS = parms.h more_managers.hpp \ ! include_osm.hpp cache.h biu.h armsim.hpp \ mach_list.hpp mang_list.hpp Index: armsim.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.hpp,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** armsim.hpp 19 Aug 2005 03:15:05 -0000 1.4 --- armsim.hpp 21 Aug 2005 04:23:12 -0000 1.5 *************** *** 20,25 **** namespace simulator { - typedef class bus_interface BIU; - /* forward declaration */ class device_emulator; --- 20,23 ---- *************** *** 50,54 **** * @param verbose Verbose mode */ ! arm_simulator(bool verbose, bool need_fpe, bool emulate_syscall); /** Destructor. */ --- 48,61 ---- * @param verbose Verbose mode */ ! arm_simulator(bool verbose, bool need_fpe, bool emulate_syscall, ! int n_ic_blk=nICacheBlocks, int n_ic_assoc=nICacheAssoc, ! int n_ic_bsize=ICacheLineSize, ! int n_dc_blk=nDCacheBlocks, int n_dc_assoc=nDCacheAssoc, ! int n_dc_bsize=DCacheLineSize, ! int n_itlb_blk=nITLBBlocks, int n_itlb_assoc=nITLBAssoc, ! int n_itlb_psize=IPageSize, ! int n_dtlb_blk=nDTLBBlocks, int n_dtlb_assoc=nDTLBAssoc, ! int n_dtlb_psize=DPageSize, int n_tlb_lat=tlbLoadLatency, ! emulator::memory *mem=NULL, bus_interface *biu=NULL); /** Destructor. */ *************** *** 161,164 **** --- 168,172 ---- /* memory saving the real data value */ emulator::memory *mem; + bus_interface *biu; /* the token managers */ *************** *** 235,238 **** --- 243,247 ---- bool emu_syscall; + bool use_self_mem; int retcode; // valid on ST_EXIT *************** *** 275,279 **** ITLB *itlb; DTLB *dtlb; - BIU *biu; mcu *imcu; mcu *dmcu; --- 284,287 ---- Index: checker.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/checker.cpp,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** checker.cpp 19 Aug 2005 03:15:05 -0000 1.1 --- checker.cpp 21 Aug 2005 04:23:12 -0000 1.2 *************** *** 164,167 **** --- 164,168 ---- delete sima; + delete ema; } else usage(argv[0]); --- NEW FILE: biu.cpp --- #include "emumem.h" #include "cache.h" #include "biu.h" using std::vector; using namespace emulator; using namespace simulator; void bus_interface::smp_service_read(cache *cash, target_addr_t addr, unsigned size, void *ptr) { vector<cache *>::iterator cit; for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) { if ((*cit)->is_block_dirty(addr)) { uint8_t *pval = (*cit)->biu_flush(addr); if (pval) { // flush occurs // assuming sizes to be the same !!! mem->write_block(addr, pval, size); delay += write_latency; break; } } } mem->read_block(ptr, addr, size); } void bus_interface::smp_service_write(cache *cash, target_addr_t addr) { // need to invalidate all caches containing the address vector<cache *>::iterator cit; for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) { (*cit)->biu_invalidate(addr); } } --- BIU.h DELETED --- |
|
From: Wei Q. <wei...@us...> - 2005-08-19 03:15:17
|
Update of /cvsroot/simit-arm/simit-arm/simulator/src In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv10309/src Modified Files: arm.mad syscall.mad Log Message: Reorganizes cache, no longer uses template but uses C++ abstraction: a base cache class and derived classes. Cache now holds real data. Changes the syscall interpreter to account for this. Changes memory read/write handling by introducing mcu. Index: syscall.mad =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/src/syscall.mad,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** syscall.mad 25 Dec 2004 18:38:55 -0000 1.2 --- syscall.mad 19 Aug 2005 03:15:07 -0000 1.3 *************** *** 24,44 **** TRANS ! e_id_ex: {ex_buffer = mEX[], v_iflag = *mCPSR[], !id_buffer}; eval_pred(pred, cond, v_iflag); e_ex_bf: {pred>0, bf_buffer = mBF[]}; ! e_bf_wb: {wb_buffer = mWB[]}; ! sys_call(imm); # execute syscall till pipeline empty ! e_wb_in: {!wb_buffer, !bf_buffer, !ex_buffer}; ! e_ex_bf_null: {pred==0, bf_buffer = mBF[], !!ex_buffer}; e_bf_wb_null: {wb_buffer = mWB[], !!bf_buffer}; e_wb_in_null: {!!wb_buffer}; ! e_ex_in: {*mReset[], !!ex_buffer}; OPERATION fpe --- 24,44 ---- TRANS ! e_id_ex: {ex_buffer = mEX[], v_iflag = *mCPSR[]}; eval_pred(pred, cond, v_iflag); e_ex_bf: {pred>0, bf_buffer = mBF[]}; ! e_bf_wb: {wb_buffer = mWB[], sc_buffer = mSC[imm]}; ! e_wb_in: {!sc_buffer, !wb_buffer, !bf_buffer, !ex_buffer, !id_buffer}; ! e_ex_bf_null: {pred==0, bf_buffer = mBF[], !!ex_buffer, !!id_buffer}; e_bf_wb_null: {wb_buffer = mWB[], !!bf_buffer}; e_wb_in_null: {!!wb_buffer}; ! e_ex_in: {*mReset[], !!ex_buffer, !!id_buffer}; + ## OPERATION fpe *************** *** 69,74 **** --- 69,158 ---- e_ex_in: {*mReset[], !!ex_buffer}; + ## + + OPERATION coproc_inst + + VAR cp_oper : {cdp, mcr, mrc, ldc, stc}; + + SYNTAX cp_oper; + CODING cp_oper; + + EVAL +cp_oper; + + TRANS + e_id_ex: {ex_buffer = mEX[], v_iflag = *mCPSR[]}; + eval_pred(pred, cond, v_iflag); + + e_ex_bf: {pred>0, bf_buffer = mBF[]}; + + e_bf_wb: {wb_buffer = mWB[], cp_buffer = mCoProc[iw]}; + + e_wb_in: {!cp_buffer, !wb_buffer, !bf_buffer, !ex_buffer, !id_buffer}; + + e_ex_bf_null: {pred==0, bf_buffer = mBF[], !!ex_buffer, !!id_buffer}; + e_bf_wb_null: {wb_buffer = mWB[], !!bf_buffer}; + e_wb_in_null: {!!wb_buffer}; + + e_ex_in: {*mReset[], !!ex_buffer, !!id_buffer}; + + + OPERATION cdp + + VAR cp_num:uint<4>; + opcd1:uint<4>; + opcd2:uint<3>; + + SYNTAX "cdp"^cond_names[cond] "p"^cp_num ^"," opcd1 ^"," + "cr"^rd ^"," "cr"^rn ^"," "cr"^rm ^"," opcd2; + + CODING cond 1110 opcd1 rn rd cp_num opcd2 0 rm; + + + OPERATION mcr + + VAR cp_num:uint<4>; + opcd1:uint<3>; + opcd2:uint<3>; + + SYNTAX "mcr"^cond_names[cond] "p"^cp_num ^"," opcd1 ^"," + reg_names[rd] ^"," "cr"^rn ^"," "cr"^rm ^"," opcd2; + + CODING cond 1110 opcd1 0 rn rd cp_num opcd2 1 rm; + + + OPERATION mrc + + VAR cp_num:uint<4>; + opcd1:uint<3>; + opcd2:uint<3>; + + SYNTAX "mrc"^cond_names[cond] "p"^cp_num ^"," opcd1 ^"," + reg_names[rd] ^"," "cr"^rn ^"," "cr"^rm ^"," opcd2; + + CODING cond 1110 opcd1 1 rn rd cp_num opcd2 1 rm; + OPERATION ldc + + VAR cp_num:uint<4>; + offset:uint<8>; + + SYNTAX "ldc"^cond_names[cond] "p"^cp_num ^"," "cr"^rd ^", ..."; + + CODING cond 110----1 rn rd cp_num offset; + + + OPERATION stc + + VAR cp_num:uint<4>; + offset:uint<8>; + + SYNTAX "stc"^cond_names[cond] "p"^cp_num ^"," "cr"^rd ^", ..."; + + CODING cond 110----0 rn rd cp_num offset; + + + + ## OPERATION coproc_ld *************** *** 117,119 **** e_ex_in: {*mReset[], !!ex_buffer}; ! --- 201,203 ---- e_ex_in: {*mReset[], !!ex_buffer}; ! ## Index: arm.mad =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/src/arm.mad,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** arm.mad 25 Dec 2004 18:38:55 -0000 1.2 --- arm.mad 19 Aug 2005 03:15:07 -0000 1.3 *************** *** 84,88 **** # reset manager, written by all operation writing to gpr reset_manager : void -> (uint<4>, uint<1>); ! coproc_manager : (uint<1>, uint<1>) -> void; INSTANCE --- 84,89 ---- # reset manager, written by all operation writing to gpr reset_manager : void -> (uint<4>, uint<1>); ! coproc_manager : uint<32> -> void; ! syscall_manager: uint<24> -> void; INSTANCE *************** *** 109,112 **** --- 110,114 ---- mCoProc : coproc_manager; + mSC : syscall_manager; *************** *** 179,182 **** --- 181,185 ---- cp_buffer : coproc_manager; + sc_buffer : syscall_manager; # states for lds/stm operations *************** *** 261,266 **** store_imm, store_reg, store_ext_imm, store_ext_reg, swap, ldm, stm, ! mult, mult_long, syscall, fpe, ! coproc_ld, coproc_st}(unknown); # unknown as the default rec:{fetch}; --- 264,269 ---- store_imm, store_reg, store_ext_imm, store_ext_reg, swap, ldm, stm, ! mult, mult_long, syscall, ! coproc_inst}(unknown); # unknown as the default rec:{fetch}; |
|
From: Wei Q. <wei...@us...> - 2005-08-19 03:15:16
|
Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv10309 Modified Files: BIU.h Makefile.am armsim.cpp armsim.hpp cache.h fetch_oper_pat.hpp fetch_oper_tab.hpp machines.cpp machines.hpp main.cpp mang_list.hpp more_managers.cpp more_managers.hpp Added Files: checker.cpp mcu.hpp Log Message: Reorganizes cache, no longer uses template but uses C++ abstraction: a base cache class and derived classes. Cache now holds real data. Changes the syscall interpreter to account for this. Changes memory read/write handling by introducing mcu. Index: machines.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/machines.hpp,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** machines.hpp 12 Nov 2004 06:33:02 -0000 1.2 --- machines.hpp 19 Aug 2005 03:15:05 -0000 1.3 *************** *** 1243,1254 **** L_$S_EX$38081, /*1229*/ L_$S_BF$38083, /*1230*/ ! L_$S_ID$38150, /*1231*/ ! L_$S_EX$38151, /*1232*/ ! L_$S_BF$38153, /*1233*/ ! L_$S_ID$38220, /*1234*/ ! L_$S_EX$38221, /*1235*/ ! L_$S_ID$38290, /*1236*/ ! L_$S_EX$38291, /*1237*/ ! L_$S_BF$38293, /*1238*/ }; --- 1243,1254 ---- L_$S_EX$38081, /*1229*/ L_$S_BF$38083, /*1230*/ ! L_$S_WB$38100, /*1231*/ ! L_$S_ID$38150, /*1232*/ ! L_$S_ID$38220, /*1233*/ ! L_$S_ID$38290, /*1234*/ ! L_$S_ID$38360, /*1235*/ ! L_$S_ID$38430, /*1236*/ ! L_$S_EX$38431, /*1237*/ ! L_$S_BF$38433, /*1238*/ }; *************** *** 1890,1901 **** bool L_$e_id_ex$38105(); bool L_$e_bf_wb$38128(); ! bool L_$e_id_ex$38175(); ! bool L_$e_ex_bf$38179(); ! bool L_$e_bf_wb$38198(); ! bool L_$e_id_ex$38245(); ! bool L_$e_ex_bf$38249(); ! bool L_$e_id_ex$38315(); ! bool L_$e_ex_bf$38319(); ! bool L_$e_bf_wb$38338(); --- 1890,1897 ---- bool L_$e_id_ex$38105(); bool L_$e_bf_wb$38128(); ! bool L_$e_wb_in$38146(); ! bool L_$e_id_ex$38455(); ! bool L_$e_ex_bf$38459(); ! bool L_$e_bf_wb$38478(); *************** *** 1944,1947 **** --- 1940,1944 ---- _UINT_T(10) C_34; _UINT_T(64) C_35; + _UINT_T(3) C_36; _UINT_T(32) _temp_coding; *************** *** 1996,1999 **** --- 1993,1997 ---- _MANG_CLASS(regfile_manager)::TOKEN_T *B_dst15; _MANG_CLASS(coproc_manager)::TOKEN_T *B_cp_buffer; + _MANG_CLASS(syscall_manager)::TOKEN_T *B_sc_buffer; #endif void __dec_0(); *************** *** 2545,2548 **** --- 2543,2548 ---- void __dec_546(); void __dec_547(); + void __dec_548(); + void __dec_549(); }; Index: more_managers.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/more_managers.hpp,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** more_managers.hpp 12 Nov 2004 06:40:32 -0000 1.3 --- more_managers.hpp 19 Aug 2005 03:15:05 -0000 1.4 *************** *** 21,31 **** namespace simulator { /* forward declaration*/ ! typedef class rcache<nICacheBlocks, nICacheAssoc, ! ICacheLineSize, memoryReadLatency> ICache; ! typedef class rwcache<nDCacheBlocks, nDCacheAssoc, ! DCacheLineSize, memoryReadLatency, memoryWriteLatency> DCache; ! typedef class rcache<nITLBBlocks, nITLBAssoc, IPageSize, tlbLoadLatency> ITLB; ! typedef class rcache<nDTLBBlocks, nDTLBAssoc, DPageSize, tlbLoadLatency> DTLB; /** The register file. */ --- 21,31 ---- namespace simulator { + class mcu; + /* forward declaration*/ ! typedef class rcache ICache; ! typedef class rwcache DCache; ! typedef class tlb ITLB; ! typedef class tlb DTLB; /** The register file. */ *************** *** 298,302 **** fetch_manager(const std::string& name) : name(name), token(new TOKEN_T(this)), ! fetch_status(0), trigger(false) {} /** Destructor. */ --- 298,302 ---- fetch_manager(const std::string& name) : name(name), token(new TOKEN_T(this)), ! status(0), trigger(false) {} /** Destructor. */ *************** *** 324,328 **** */ bool token_good_to_reclaim(TOKEN_T *token, _BASE_MACHINE *obj) { ! return fetch_status==0; } --- 324,328 ---- */ bool token_good_to_reclaim(TOKEN_T *token, _BASE_MACHINE *obj) { ! return status==0; } *************** *** 332,336 **** TOKEN_T *allocate_token(_BASE_MACHINE *obj) { token->set_used(obj); ! fetch_status = 1; trigger = true; return token; --- 332,336 ---- TOKEN_T *allocate_token(_BASE_MACHINE *obj) { token->set_used(obj); ! status = 1; trigger = true; return token; *************** *** 365,373 **** _UINT_T(32) read_token(_BASE_MACHINE *obj, TOKEN_T *token) { - unsigned iw = mem->read_word_fast(current_pc); - #ifdef DEBUG - //fprintf(stderr, "0x%08x\n", current_pc); - fprintf(stderr, "0x%08x : 0x%08x\n", current_pc, iw); - #endif return iw; } --- 365,368 ---- *************** *** 375,389 **** /** Connect the fetcher with other modules. * @param mrf The register file manager, for program counter. ! * @param csh The instruction cache object. ! * @param tlb The instruction tlb object. ! * @param imm The memory to get instrution from. */ ! void connect(regfile_manager *mrf, reset_manager *mrs, ! ICache *csh, ITLB *tlb, emulator::memory *imm) { mRF = mrf; mRS = mrs; ! icache = csh; ! itlb = tlb; ! mem = imm; } --- 370,380 ---- /** Connect the fetcher with other modules. * @param mrf The register file manager, for program counter. ! * @param mrs The reset manager. ! * @param csh The instruction memory controller. */ ! void connect(regfile_manager *mrf, reset_manager *mrs, mcu *csh) { mRF = mrf; mRS = mrs; ! imcu = csh; } *************** *** 395,401 **** trigger = false; token->set_unused(); ! fetch_status = 0; } private: --- 386,397 ---- trigger = false; token->set_unused(); ! status = 0; ! branch_taken = false; ! first_inst = true; } + /** get the current pc */ + unsigned get_current_pc(); + private: *************** *** 404,416 **** unsigned current_pc; /* the pc currently fetching */ ! int fetch_status; /* state of fetching. */ int trigger; /* start a new request. */ /* connected components. */ regfile_manager *mRF; reset_manager *mRS; ! ICache *icache; ! ITLB *itlb; ! emulator::memory *mem; }; --- 400,415 ---- unsigned current_pc; /* the pc currently fetching */ ! int status; /* state of fetching. */ int trigger; /* start a new request. */ + word_t iw; /* connected components. */ regfile_manager *mRF; reset_manager *mRS; ! mcu *imcu; ! ! // two flags for debugging ! int branch_taken, first_inst; ! }; *************** *** 432,436 **** */ mem_ctrl_port(const std::string& name) : ! name(name), count(0), status(0), mergeable(false), trigger(false) {} /** Destructor. */ --- 431,435 ---- */ mem_ctrl_port(const std::string& name) : ! name(name), count(0), status(0), trigger(false) {} /** Destructor. */ *************** *** 473,492 **** /** Connect the module with other modules. ! * @param csh The data cache object. ! * @param tlb The data tlb object. * @param rpt The memory read port. * @param wpt The memory write port. - * @param dmm The data memory containing real data. * @param map The memory address port. * @param reg The register file. */ ! void connect(DCache *csh, DTLB *tlb, ! mem_read_port *rpt, mem_write_port *wpt, emulator::memory *dmm, mem_addr_port *map, regfile_manager *reg) { ! dcache = csh; ! dtlb = tlb; mMemRead = rpt; mMemWrite = wpt; - mem = dmm; mMemAddr = map; mRF = reg; --- 472,487 ---- /** Connect the module with other modules. ! * @param csh The data memory controller. * @param rpt The memory read port. * @param wpt The memory write port. * @param map The memory address port. * @param reg The register file. */ ! void connect(mcu *csh, ! mem_read_port *rpt, mem_write_port *wpt, mem_addr_port *map, regfile_manager *reg) { ! dmcu = csh; mMemRead = rpt; mMemWrite = wpt; mMemAddr = map; mRF = reg; *************** *** 499,502 **** --- 494,498 ---- void reset() { status = 0; + count = 0; } *************** *** 509,523 **** unsigned addr; unsigned size; - bool mergeable; bool isRead; bool trigger; ! DCache *dcache; ! DTLB *dtlb; mem_read_port *mMemRead; mem_write_port *mMemWrite; mem_addr_port *mMemAddr; regfile_manager *mRF; - emulator::memory *mem; }; --- 505,518 ---- unsigned addr; unsigned size; bool isRead; bool trigger; ! uint32_t val; ! ! mcu *dmcu; mem_read_port *mMemRead; mem_write_port *mMemWrite; mem_addr_port *mMemAddr; regfile_manager *mRF; }; *************** *** 711,742 **** }; ! class coproc_manager { public: /** index type. */ ! typedef _TUPLE_T(_UINT_T(1),_UINT_T(1)) I; /** token type. */ ! typedef class _token_<coproc_manager> TOKEN_T; /** Constructor. * @param name Name of the register file */ ! coproc_manager(const std::string& name) : name(name), state(0) { token = new TOKEN_T(this); } /** Destructor. */ ! ~coproc_manager() { delete token; } ! /** See if token is available for inquire. * @param ind The index of the token. * @param obj The OSM sending the request. */ bool token_free_for_alloc(const I& ind, _BASE_MACHINE *obj) { ! return token->is_free(); } --- 706,738 ---- }; ! class syscall_manager { public: /** index type. */ ! typedef _UINT_T(24) I; /** token type. */ ! typedef class _token_<syscall_manager> TOKEN_T; /** Constructor. * @param name Name of the register file */ ! syscall_manager(const std::string& name) : name(name) { token = new TOKEN_T(this); + reset(); } /** Destructor. */ ! ~syscall_manager() { delete token; } ! /** See if token is available for allocation. * @param ind The index of the token. * @param obj The OSM sending the request. */ bool token_free_for_alloc(const I& ind, _BASE_MACHINE *obj) { ! return true; } *************** *** 746,750 **** */ bool token_good_to_reclaim(TOKEN_T *token, _BASE_MACHINE *obj) { ! return state==0; } --- 742,746 ---- */ bool token_good_to_reclaim(TOKEN_T *token, _BASE_MACHINE *obj) { ! return !busy; } *************** *** 754,759 **** */ TOKEN_T *allocate_token(const I& ind, _BASE_MACHINE *obj) { ! state = ind.first.val()?2:1; ! has_addr = ind.second.val(); return token; } --- 750,755 ---- */ TOKEN_T *allocate_token(const I& ind, _BASE_MACHINE *obj) { ! sc_num = ind.val() & 0x3FF; ! trigger = busy = true; return token; } *************** *** 769,773 **** /** Discard a token. * @param token The token to discard. ! * @param obj The OSM sending the request. */ void discard_token(TOKEN_T *token, _BASE_MACHINE *obj) { --- 765,769 ---- /** Discard a token. * @param token The token to discard. ! * @param obj The OSM sending the request. */ void discard_token(TOKEN_T *token, _BASE_MACHINE *obj) { *************** *** 780,808 **** } ! /** Connect the fetcher with other modules. ! * @param mrf The register file manager, for program counter. ! * @param imm The memory to get instrution from. */ ! void connect(regfile_manager *mrf, emulator::memory *imm) { ! mRF = mrf; ! mem = imm; } ! /** Register the device master . */ ! void register_dev_master(emulator::device_master *dev) { ! dev_emul = dev; } ! /** Free those temporarily allocated. */ ! void update_on_clock() { ! if (state==0) return; ! else if (state==1) do_read(); ! else do_write(); } /** Resetting states. */ void reset() { - state = 0; token->set_unused(); } --- 776,888 ---- } ! void update_on_clock(); ! ! /** Resetting states. */ ! void reset() { ! token->set_unused(); ! trigger = in_fpe = busy = false; ! } ! ! void set_armsim(arm_simulator *armsim) { ! _armsim = armsim; ! } ! ! private: ! ! std::string name; ! ! TOKEN_T *token; ! unsigned sc_num; ! ! bool in_fpe; ! bool busy; ! bool trigger; ! ! // for access to cycle count ! arm_simulator *_armsim; ! }; ! ! class coproc_manager { ! ! public: ! ! /** index type. */ ! typedef _UINT_T(32) I; ! ! /** token type. */ ! typedef class _token_<coproc_manager> TOKEN_T; ! ! /** Constructor. ! * @param name Name of the register file */ ! coproc_manager(const std::string& name) : name(name) { ! token = new TOKEN_T(this); ! reset(); } ! /** Destructor. */ ! ~coproc_manager() { ! delete token; } ! /** See if token is available for allocation. ! * @param ind The index of the token. ! * @param obj The OSM sending the request. ! */ ! bool token_free_for_alloc(const I& ind, _BASE_MACHINE *obj) { ! return true; ! } ! ! /** See if it is ok to release token. ! * @param token The token to release. ! * @param obj The OSM sending the request. ! */ ! bool token_good_to_reclaim(TOKEN_T *token, _BASE_MACHINE *obj) { ! return !busy; } + /** Allocate a token. + * @param ind The index of the token. + * @param obj The OSM sending the request. + */ + TOKEN_T *allocate_token(const I& ind, _BASE_MACHINE *obj) { + iw = ind.val(); + trigger = true; + #ifndef ENABLE_CP + fprintf(stderr, "Coprocessor instruction ignored 0x%08x!\n", iw); + #endif + return token; + } + + /** Release a token. + * @param token The token to release. + * @param obj The OSM sending the request. + */ + void reclaim_token(TOKEN_T *token, _BASE_MACHINE *obj) { + } + + /** Discard a token. + * @param token The token to discard. + * @param obj The OSM sending the request. + */ + void discard_token(TOKEN_T *token, _BASE_MACHINE *obj) { + } + + /** Get the name of the manager. */ + const std::string& get_name() { + return name; + } + + void trigger_coproc(); + void update_on_clock(); + /** Resetting states. */ void reset() { token->set_unused(); + trigger = busy = false; + } + + void set_armsim(arm_simulator *armsim) { + _armsim = armsim; } *************** *** 810,827 **** std::string name; - TOKEN_T *token; - - regfile_manager *mRF; - emulator::memory *mem; ! bool has_addr; // has address or not ! int state; // 0: nothing, 1 to read, 2 to write ! emulator::device_master *dev_emul; ! void do_read(); ! void do_write(); }; } --- 890,905 ---- std::string name; ! TOKEN_T *token; ! uint32_t iw; ! bool busy; ! bool trigger; ! // for access to cycle count ! arm_simulator *_armsim; }; + } Index: more_managers.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/more_managers.cpp,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** more_managers.cpp 12 Nov 2004 06:33:02 -0000 1.2 --- more_managers.cpp 19 Aug 2005 03:15:05 -0000 1.3 *************** *** 1,4 **** --- 1,5 ---- #include "more_managers.hpp" + #include "mcu.hpp" #include "armsim.hpp" #include "emu_device.hpp" *************** *** 6,12 **** --- 7,44 ---- using namespace simulator; + + unsigned fetch_manager::get_current_pc() + { + #ifdef ARMSIM_SERIALIZE + if (branch_taken | first_inst) + return mRF->get_pc().val(); + else + return mRF->get_pc().val()-4; + #else + return mRF->get_pc().val(); + #endif + } + void fetch_manager::update_on_clock() { + /* for debugging use, disables pipelining */ + #ifdef ARMSIM_SERIALIZE + if (mRS->branch_taken()) + branch_taken = 1; + #endif + /* a new OSM comes in */ + #ifdef ARMSIM_SERIALIZE + if (trigger) { + if (branch_taken | first_inst) + current_pc = mRF->get_pc().val(); + else + current_pc = mRF->get_pc().val()-4; + branch_taken = 0; + mRF->set_pc(current_pc+8); + trigger = false; + first_inst = 0; + } + #else if (trigger) { current_pc = mRF->get_pc().val(); *************** *** 14,27 **** trigger = false; } ! if (fetch_status==1) { ! if (itlb->read(current_pc, 4)) { ! fetch_status = 2; ! } } ! if (fetch_status==2) { ! if (icache->read(current_pc, 4)) { ! fetch_status = 0; ! } } } --- 46,61 ---- trigger = false; } + #endif ! if (status==1 && !imcu->is_busy()) { ! imcu->start_read(current_pc, &iw, 4); ! status = 2; } ! if (status==2 && !imcu->is_busy()) { ! status = 0; ! #ifdef DEBUG ! //fprintf(stderr, "0x%08x\n", current_pc); ! fprintf(stderr, "0x%08x : 0x%08x\n", current_pc, iw); ! #endif } } *************** *** 30,39 **** { if (trigger) { - assert(status==0); status = 1; - addr = mMemAddr->get_value().val(); - mergeable = count > 0; trigger = false; } else if (count>0) { --- 64,71 ---- { if (trigger) { assert(status==0); status = 1; trigger = false; + addr = mMemAddr->get_value().val(); } else if (count>0) { *************** *** 45,128 **** } ! if (status==1) { ! if (dtlb->read(addr, size)) ! status = 2; } ! if (status==2) { ! if (isRead && dcache->read(addr, size)) { ! if (size==4) { ! mMemRead->set_value(mem->read_word(addr)); ! } ! else if (size==1) { ! mMemRead->set_value(mem->read_byte(addr)); ! } ! else { ! mMemRead->set_value(mem->read_half_word(addr)); ! } ! status = 0; ! #if 0 ! std::cerr << "read once " << std::hex << addr << " " ! << mMemRead->get_value() << " " ; #endif ! } ! if (!isRead && dcache->write(addr, size, mergeable)) { ! if (size==4) { ! mem->write_word(addr, mMemWrite->get_value().val()); ! } ! else if (size==1) { ! mem->write_byte(addr, mMemWrite->get_value().val()); ! } ! else { ! mem->write_half_word(addr, mMemWrite->get_value().val()); ! } ! status = 0; #if 0 ! std::cerr << "write once " << std::hex << addr << " " ! << mMemWrite->get_value() << " " ; #endif - } - } } ! void coproc_manager::do_read() { ! // r0 contains the device id ! dev_id_t id = mRF->get_value(0).val(); ! // r1 contains the address ! dev_addr_t addr = mRF->get_value(1).val(); ! dev_data_t data; ! if (has_addr) { ! if (dev_emul->receive(id, data, addr)) { ! state = 0; ! mRF->set_value(0, data); ! } ! } ! else if (dev_emul->receive(id, data)) { ! state = 0; ! mRF->set_value(0, data); ! } } ! void coproc_manager::do_write() { ! // r0 contains the device id ! dev_id_t id = mRF->get_value(0).val(); ! // r2 contains the address ! dev_addr_t addr = mRF->get_value(2).val(); ! // r1 contains the value to write ! dev_data_t data = mRF->get_value(1).val(); ! if (has_addr) { ! if (dev_emul->send(id, data, addr)) ! state = 0; } ! else if (dev_emul->send(id, data)) { ! state = 0; } } --- 77,228 ---- } ! // step 1, waiting for MMU to be available ! if (status==1 && !dmcu->is_busy()) { ! ! if (isRead) ! dmcu->start_read(addr, &val, size); ! else { ! val = mMemWrite->get_value().val(); ! dmcu->start_write(addr, &val, size); ! } ! ! status = 2; } ! // step 2, waiting for MMU to finish ! if (status==2 && !dmcu->is_busy()) { ! if (isRead) mMemRead->set_value(val); ! status = 0; ! #ifdef DEBUG ! if (size==1) val = val&0xFF; ! else if (size==2) val = val&0xFFFF; ! fprintf(stderr, "mem %d %x %x\n", isRead, addr, val); #endif ! } ! } ! ! void syscall_manager::update_on_clock() ! { ! if (trigger) { ! trigger = false; ! _armsim->syscall_start(sc_num); ! busy = true; ! } ! else if (busy) { ! busy = _armsim->syscall_busy(); ! } ! } ! ! #if 0 ! ! void sfu2x2_manager::read_value(unsigned index, uint32_t &val1, uint32_t &val2) ! { ! #ifdef ENABLE_SFU ! _armsim->sfu2x2_read(index, val1, val2); ! //fprintf(stderr, "read value %d %d %d\n", index, val1, val2); #endif } ! void sfu2x2_manager::write_value(unsigned index, uint32_t val1, uint32_t val2) { ! #ifdef ENABLE_SFU ! _armsim->sfu2x2_write(index, val1, val2); ! //fprintf(stderr, "write value %d %d %d\n", index, val1, val2); ! #endif ! } ! void sfu3x1_manager::read_value(unsigned index, uint32_t &val) ! { ! #ifdef ENABLE_SFU ! _armsim->sfu3x1_read(index, val); ! //fprintf(stderr, "read value %d %d\n", index, val); ! #endif ! } ! void sfu3x1_manager::write_value(unsigned index, uint32_t val1, ! uint32_t val2, uint32_t val3) ! { ! #ifdef ENABLE_SFU ! _armsim->sfu3x1_write(index, val1, val2, val3); ! //fprintf(stderr, "write value %d %d %d\n", index, val1, val2); ! #endif ! } ! void sfu2x1_manager::read_value(unsigned index, uint32_t &val) ! { ! #ifdef ENABLE_SFU ! _armsim->sfu2x1_read(index, val); ! //fprintf(stderr, "read value %d %d\n", index, val); ! #endif } ! void sfu2x1_manager::write_value(unsigned index, uint32_t val1, uint32_t val2) { ! #ifdef ENABLE_SFU ! _armsim->sfu2x1_write(index, val1, val2); ! //fprintf(stderr, "write value %d %d %d\n", index, val1, val2); ! #endif ! } ! #endif ! void coproc_manager::update_on_clock() ! { ! #ifdef ENABLE_CP ! if (trigger) { ! trigger = false; ! busy = true; ! _armsim->coproc_start(iw); } ! else if (busy) { ! busy = _armsim->coproc_busy(); ! ! if (!busy) { ! arm_simulator::CP_FLAG flag = _armsim->coproc_status(); ! switch (flag) { ! case arm_simulator::CP_FLAG_NORMAL: ! //good, do nothing ! break; ! case arm_simulator::CP_FLAG_ILLEGAL: ! fprintf(stderr, "Illegal " ! "coprocessor instruction 0x%08x\n", iw); ! break; ! case arm_simulator::CP_FLAG_NO_ACK: ! fprintf(stderr, "Error processing coprocessor " ! "instruction 0x%08x : " ! "no coprocessor responds\n", iw); ! break; ! case arm_simulator::CP_FLAG_WRITE_PC: ! fprintf(stderr, "Illegal coprocessor " ! "instruction 0x%08x : " ! "writing to PC\n", iw); ! break; ! case arm_simulator::CP_FLAG_ERROR: ! fprintf(stderr, "Error processing " ! "coprocessor instruction 0x%08x\n", iw); ! break; ! case arm_simulator::CP_FLAG_OVERFLOW: ! fprintf(stderr, "Abnormal coprocessor behavior " ! "for instruction 0x%08x : " ! " more than 16 memory references.\n", iw); ! raise(SIGINT); ! break; ! case arm_simulator::CP_FLAG_EARLY_DONE: ! fprintf(stderr, "Abnormal coprocessor behavior " ! "for instruction 0x%08x : " ! "done signal earlier than expected.\n", iw); ! raise(SIGINT); ! break; ! case arm_simulator::CP_FLAG_TIME_OUT: ! fprintf(stderr, "Abnormal coprocessor behavior " ! "for instruction 0x%08x : " ! "time out.\n", iw); ! raise(SIGINT); ! break; ! } ! } } + #endif } Index: cache.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/cache.h,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** cache.h 21 May 2005 20:28:48 -0000 1.4 --- cache.h 19 Aug 2005 03:15:05 -0000 1.5 *************** *** 4,332 **** #include <string> #include "BIU.h" namespace simulator { ! struct cache_block { ! uint32_t tag; ! bool valid; ! bool dirty[2]; [...997 lines suppressed...] ! target_addr_t flush_addr; // flush addr ! ! enum { ! IDLE, ! PENDING_FLUSH, ! WAITING_FLUSH, ! PENDING_LOAD, ! WAITING_LOAD ! } state; ! ! uint64_t nReads, nReadMisses; ! uint64_t nWrites, nWriteMisses; ! ! bool flush_only; ! ! tag_t *reqTag; ! struct data_t *reqLine; ! struct data_t *values; //[n_block/n_assoc][n_assoc]; }; Index: armsim.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.cpp,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** armsim.cpp 20 May 2005 06:11:27 -0000 1.5 --- armsim.cpp 19 Aug 2005 03:15:05 -0000 1.6 *************** *** 2,5 **** --- 2,6 ---- #include "armsim.hpp" #include "more_managers.hpp" + #include "mcu.hpp" #include "machines.hpp" *************** *** 28,39 **** { /* create the hardware modules */ ! biu = new BIU("biu"); ! icache = new ICache("icache", *biu); ! itlb = new ITLB("itlb", *biu); ! dcache = new DCache("dcache", *biu); ! dtlb = new DTLB("dtlb", *biu); ! mem = new memory(); /* Create the managers */ --- 29,45 ---- { + mem = new memory(); + /* create the hardware modules */ ! biu = new BIU("biu", mem, memoryReadLatency, memoryWriteLatency); ! icache = new ICache("icache", nICacheBlocks, nICacheAssoc, ICacheLineSize, ! biu); ! dcache = new DCache("dcache", nDCacheBlocks, nDCacheAssoc, DCacheLineSize, ! biu); ! itlb = new ITLB("itlb", nITLBBlocks, nITLBAssoc, IPageSize, tlbLoadLatency); ! dtlb = new DTLB("dtlb", nDTLBBlocks, nDTLBAssoc, DPageSize, tlbLoadLatency); ! imcu = new mcu("imcu", itlb, icache); ! dmcu = new mcu("dmcu", dtlb, dcache); /* Create the managers */ *************** *** 42,52 **** /* conenct the managers. */ ! mIF->connect(mRF, mReset, icache, itlb, mem); ! mMemCtrl->connect(dcache, dtlb, mMemRead, mMemWrite, mem, mMemAddr, mRF); mNewPC->connect(mRF); ! mCoProc->connect(mRF, mem); dev_master = new device_master(); ! mCoProc->register_dev_master(dev_master); init_devices(dev_master); --- 48,61 ---- /* conenct the managers. */ ! mIF->connect(mRF, mReset, imcu); ! mMemCtrl->connect(dmcu, mMemRead, mMemWrite, mMemAddr, mRF); mNewPC->connect(mRF); ! mSC->set_armsim(this); ! mCoProc->set_armsim(this); ! ! //mCoProc->connect(mRF, mem); dev_master = new device_master(); ! //mCoProc->register_dev_master(dev_master); init_devices(dev_master); *************** *** 54,57 **** --- 63,68 ---- machine_pool = new obj_pool<_opt_machine_, _MACH_ID_T, arm_simulator, arm_simulator::mach_allocator>(_mach_total); + + syscall_buf = NULL; /* reset every thing */ *************** *** 61,64 **** --- 72,80 ---- arm_simulator::~arm_simulator() { + // flush the pipeline + for (work_it=work_list.begin(); work_it!=work_list.end();) { + sink_machine(*work_it); + work_it = work_list.erase(work_it); + } delete machine_pool; *************** *** 75,78 **** --- 91,100 ---- delete dtlb; delete mem; + + delete imcu; + delete dmcu; + + if (syscall_buf) free(syscall_buf); + } *************** *** 80,87 **** { mem->reset(); ! icache->reset(); ! dcache->reset(); ! itlb->reset(); ! dtlb->reset(); biu->reset(); --- 102,107 ---- { mem->reset(); ! imcu->reset(); ! dmcu->reset(); biu->reset(); *************** *** 101,104 **** --- 121,138 ---- status = ST_RESET; in_fpe = false; + + inst_done = false; + + syscall_phase = 0; + syscall_state = SYSCALL_IDLE; + if (syscall_buf) { + free(syscall_buf); + syscall_buf = NULL; + } + + for (work_it=work_list.begin(); work_it!=work_list.end();) { + sink_machine(*work_it); + work_it = work_list.erase(work_it); + } } *************** *** 112,120 **** void arm_simulator::dump_stats(FILE *fp) { ! icache->PrintStats(fp); ! itlb->PrintStats(fp); ! dcache->PrintStats(fp); ! dtlb->PrintStats(fp); ! biu->PrintStats(fp); fprintf(fp, "Total allocated OSMs : %lld\n", alloc_count); --- 146,154 ---- void arm_simulator::dump_stats(FILE *fp) { ! icache->print_stats(fp); ! itlb->print_stats(fp); ! dcache->print_stats(fp); ! dtlb->print_stats(fp); ! biu->print_stats(fp); fprintf(fp, "Total allocated OSMs : %lld\n", alloc_count); *************** *** 170,216 **** #undef DEBUG_CYCLE #ifdef DEBUG_CYCLE ! fprintf(stderr, "--clock %d--\n", cycle_count); #endif ! /** Activate all OSMs in order. */ ! for (work_it=work_list.begin(); work_it!=work_list.end();) { ! ins_it = work_it; ! ins_it++; #if defined DEBUG_CYCLE || defined DEBUG ! int oldstate = (*work_it)->__get_state(); #endif ! bool ret = (*work_it)->__activate(); #ifdef DEBUG_CYCLE ! std::cerr << (*work_it)->__get_dynid() << " " << oldstate << "->"; ! std::cerr << (*work_it)->__get_state() << " " << ret << std::endl; #endif ! /* Test if the OSM is back to the initial state. */ ! if (ret) { /* no */ ! work_it++; ! } ! else { /* yes */ - /* send retired ones to the sink. */ - sink_machine(*work_it); - work_it = work_list.erase(work_it); - } } ! cycle_count++; ! mMemCtrl->update_on_clock(); ! mNewPC->update_on_clock(); ! mIF->update_on_clock(); ! mReset->update_on_clock(); ! mEX->update_on_clock(); ! mCoProc->update_on_clock(); ! icache->updateOnClockTick(); ! itlb->updateOnClockTick(); ! dcache->updateOnClockTick(); ! dtlb->updateOnClockTick(); ! biu->updateOnClockTick(); } --- 204,263 ---- #undef DEBUG_CYCLE #ifdef DEBUG_CYCLE ! fprintf(stderr, "--clock %d--\n", cycle_count); #endif ! #ifdef ARMSIM_SERIALIZE ! inst_done = false; ! #endif ! /** Activate all OSMs in order. */ ! for (work_it=work_list.begin(); work_it!=work_list.end();) { ! ! ins_it = work_it; ! ins_it++; #if defined DEBUG_CYCLE || defined DEBUG ! int oldstate = (*work_it)->__get_state(); #endif ! bool ret = (*work_it)->__activate(); #ifdef DEBUG_CYCLE ! std::cerr << (*work_it)->__get_dynid() << " " << oldstate << "->"; ! std::cerr << (*work_it)->__get_state() << " " << ret << std::endl; #endif ! /* Test if the OSM is back to the initial state. */ ! if (ret) { /* no */ ! work_it++; ! } ! else { /* yes */ ! ! /* send retired ones to the sink. */ ! sink_machine(*work_it); ! work_it = work_list.erase(work_it); ! ! #ifdef ARMSIM_SERIALIZE ! inst_done = true; ! #endif } + #ifdef ARMSIM_SERIALIZE + break; + #endif + } ! cycle_count++; ! mMemCtrl->update_on_clock(); ! mNewPC->update_on_clock(); ! mIF->update_on_clock(); ! mReset->update_on_clock(); ! mEX->update_on_clock(); ! mCoProc->update_on_clock(); ! mSC->update_on_clock(); ! imcu->update_on_clock(); ! dmcu->update_on_clock(); ! biu->update_on_clock(); ! ! syscall_update(); } *************** *** 222,226 **** status = ST_RUNNING; ! while(status==ST_RUNNING && cycle_count<=maxCycle) { clock_tick(); } --- 269,273 ---- status = ST_RUNNING; ! while(status==ST_RUNNING && cycle_count<maxCycle) { clock_tick(); } *************** *** 268,269 **** --- 315,424 ---- } + + /* Syscall related functions begin */ + void arm_simulator::syscall_start(unsigned int num) + { + assert(syscall_state==SYSCALL_IDLE); + syscall_num = num; + sc_impl(this, syscall_num); + } + + void arm_simulator::syscall_update() + { + switch (syscall_state) { + + case SYSCALL_PENDING_MEM_READ: + + if (!dmcu->is_busy()) { + + syscall_state = SYSCALL_WAITING_MEM_READ; + + dmcu->start_read_block(syscall_mem_addr, + syscall_mem_ptr, syscall_mem_size); + } + break; + + case SYSCALL_WAITING_MEM_READ: + + if (!dmcu->is_busy()) { + syscall_state = SYSCALL_IDLE; + } + break; + + case SYSCALL_PENDING_MEM_WRITE: + + if (!dmcu->is_busy()) { + + syscall_state = SYSCALL_WAITING_MEM_READ; + + dmcu->start_write_block(syscall_mem_addr, + syscall_mem_ptr, syscall_mem_size); + } + break; + + case SYSCALL_WAITING_MEM_WRITE: + + if (!dmcu->is_busy()) { + syscall_state = SYSCALL_IDLE; + } + break; + + default: break; + + } + + // call syscall handler another time + if (syscall_state==SYSCALL_IDLE && syscall_phase) + sc_impl(this, syscall_num); + } + + void arm_simulator::syscall_mem_read_block(target_addr_t addr, + uint8_t *ptr, unsigned size) + { + assert(syscall_state == SYSCALL_IDLE); + assert(ptr!=NULL); + assert(size>0); + + syscall_state = SYSCALL_PENDING_MEM_READ; + syscall_mem_addr = addr; + syscall_mem_size = size; + syscall_mem_ptr = ptr; + } + + void arm_simulator::syscall_mem_write_block(target_addr_t addr, + uint8_t *ptr, unsigned size) + { + assert(syscall_state == SYSCALL_IDLE); + assert(ptr!=NULL); + assert(size>0); + + syscall_state = SYSCALL_PENDING_MEM_WRITE; + syscall_mem_addr = addr; + syscall_mem_size = size; + syscall_mem_ptr = ptr; + } + + void arm_simulator::syscall_realloc_buf(unsigned size) + { + assert(syscall_buf!=NULL); + syscall_buf = realloc(syscall_buf, size); + if (syscall_buf==NULL) { + fprintf(stderr, "Error: Out of host memory when allocating %d" + " bytes for a system call.\n", size); + exit(-1); + } + } + + void arm_simulator::syscall_alloc_buf(unsigned size) + { + if (syscall_buf!=NULL) + free(syscall_buf); + + syscall_buf = malloc(size); + if (syscall_buf==NULL) { + fprintf(stderr, "Error: Out of host memory when reallocating %d" + " bytes for a system call.\n", size); + exit(-1); + } + } + Index: Makefile.am =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/Makefile.am,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** Makefile.am 20 May 2005 06:11:27 -0000 1.3 --- Makefile.am 19 Aug 2005 03:15:05 -0000 1.4 *************** *** 1,10 **** ! bin_PROGRAMS = sima sima_SOURCES = main.cpp sima_LDADD = libarmsim.a ! AM_CPPFLAGS = -D__COMPILE_SIMULATOR_ INCLUDES = -I$(top_srcdir)/libosm -I$(top_srcdir)/emulator -I$(top_builddir)/emulator --- 1,15 ---- ! bin_PROGRAMS = sima checker sima_SOURCES = main.cpp sima_LDADD = libarmsim.a ! checker_SOURCES = checker.cpp armsim.cpp more_managers.cpp ! checker_CPPFLAGS = -DARMSIM_SERIALIZE -DCOMPILE_SIMULATOR ! checker_LDADD = libarmsim.a $(top_builddir)/emulator/libarmemu.a ! checker_LDFLAGS = -z muldefs ! ! INCLUDES = -I$(top_srcdir)/libosm -I$(top_srcdir)/emulator -I$(top_builddir)/emulator *************** *** 21,25 **** include_temp.hpp more_managers.hpp interface.hpp \ cache.h fetch_oper_dec.hpp mach_list.hpp \ ! BIU.h machines.hpp parms.h \ fetch_oper_pat.hpp fetch_oper_tab.hpp func.hpp \ $(top_builddir)/emulator/syscall.cpp \ --- 26,30 ---- include_temp.hpp more_managers.hpp interface.hpp \ cache.h fetch_oper_dec.hpp mach_list.hpp \ ! BIU.h machines.hpp parms.h mcu.h \ fetch_oper_pat.hpp fetch_oper_tab.hpp func.hpp \ $(top_builddir)/emulator/syscall.cpp \ *************** *** 33,36 **** --- 38,43 ---- $(top_builddir)/emulator/external_dev_stub.o + AM_CPPFLAGS = -DCOMPILE_SIMULATOR + include_HEADERS = parms.h more_managers.hpp \ include_osm.hpp cache.h BIU.h armsim.hpp \ Index: fetch_oper_pat.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/fetch_oper_pat.hpp,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** fetch_oper_pat.hpp 2 Mar 2005 21:46:16 -0000 1.4 --- fetch_oper_pat.hpp 19 Aug 2005 03:15:05 -0000 1.5 *************** *** 3,10 **** Input statistics ! Total entries : 1289 ! Unique labels : 548 ! Shannon entropy : 9.09208 ! Huffman tree height : 9.12751 Decoder characteristics --- 3,10 ---- Input statistics ! Total entries : 1284 ! Unique labels : 550 ! Shannon entropy : 9.10075 ! Huffman tree height : 9.13662 Decoder characteristics *************** *** 82,101 **** _STUB_DEC(stub_0_126) _STUB_DEC(stub_0_127) ! _STUB_DEC(stub_0_208) ! _STUB_DEC(stub_0_209) ! _STUB_DEC(stub_0_210) ! _STUB_DEC(stub_0_211) ! _STUB_DEC(stub_0_212) ! _STUB_DEC(stub_0_213) ! _STUB_DEC(stub_0_214) ! _STUB_DEC(stub_0_215) ! _STUB_DEC(stub_0_216) ! _STUB_DEC(stub_0_217) ! _STUB_DEC(stub_0_218) ! _STUB_DEC(stub_0_219) ! _STUB_DEC(stub_0_220) ! _STUB_DEC(stub_0_221) ! _STUB_DEC(stub_0_222) ! _STUB_DEC(stub_0_223) _STUB_DEC(stub_1_0) _STUB_DEC(stub_1_2) --- 82,101 ---- _STUB_DEC(stub_0_126) _STUB_DEC(stub_0_127) ! _STUB_DEC(stub_0_224) ! _STUB_DEC(stub_0_225) ! _STUB_DEC(stub_0_226) ! _STUB_DEC(stub_0_227) ! _STUB_DEC(stub_0_228) ! _STUB_DEC(stub_0_229) ! _STUB_DEC(stub_0_230) ! _STUB_DEC(stub_0_231) ! _STUB_DEC(stub_0_232) ! _STUB_DEC(stub_0_233) ! _STUB_DEC(stub_0_234) ! _STUB_DEC(stub_0_235) ! _STUB_DEC(stub_0_236) ! _STUB_DEC(stub_0_237) ! _STUB_DEC(stub_0_238) ! _STUB_DEC(stub_0_239) _STUB_DEC(stub_1_0) _STUB_DEC(stub_1_2) *************** *** 340,356 **** /* ! Table begin: index=0 size=1289 Mask=0x0ff00ff0 DMask=0x00000000 CMask=0x08000000 Sig=0x03000000 ! Prob=549.005 Entropy=9.09208418 HTreeHeight=9.1275125 ------------------------------------------------------------------- mask=0x0f000000 sig=0x0a000000 prob=0.00182147704 name=DEC_fetch_oper_branch_ mask=0x0f000000 sig=0x0b000000 prob=0.00182147704 name=DEC_fetch_oper_branch_link_ ! mask=0x0f000200 sig=0x0d000000 prob=0.000455369259 name=DEC_fetch_oper_fpe_ ! mask=0x0f000400 sig=0x0d000200 prob=0.000455369259 name=DEC_fetch_oper_fpe_ ! mask=0x0f000800 sig=0x0d000600 prob=0.000455369259 name=DEC_fetch_oper_fpe_ ! mask=0x0f100200 sig=0x0d100c00 prob=0.000151789753 name=DEC_fetch_oper_fpe_ ! mask=0x0f100400 sig=0x0d100a00 prob=0.000151789753 name=DEC_fetch_oper_fpe_ ! mask=0x0f100800 sig=0x0d100600 prob=0.000151789753 name=DEC_fetch_oper_fpe_ ! mask=0x0f100e00 sig=0x0d000e00 prob=0.00182147704 name=DEC_fetch_oper_coproc_st_ mask=0x0ff00000 sig=0x02a00000 prob=0.00182147704 name=DEC_fetch_oper_dpi_imm_binop_adc_ mask=0x0ff00000 sig=0x02b00000 prob=0.00182147704 name=DEC_fetch_oper_dpi_imm_binop_adcs_ --- 340,354 ---- /* ! Table begin: index=0 size=1284 Mask=0x0ff00ff0 DMask=0x00000000 CMask=0x08000000 Sig=0x03000000 ! Prob=549.005 Entropy=9.10074509 HTreeHeight=9.13661989 ------------------------------------------------------------------- mask=0x0f000000 sig=0x0a000000 prob=0.00182147704 name=DEC_fetch_oper_branch_ mask=0x0f000000 sig=0x0b000000 prob=0.00182147704 name=DEC_fetch_oper_branch_link_ ! mask=0x0f000010 sig=0x0e000000 prob=0.00182147704 name=DEC_fetch_oper_coproc_inst_cdp_ ! mask=0x0e100000 sig=0x0c100000 prob=0.00182147704 name=DEC_fetch_oper_coproc_inst_ldc_ ! mask=0x0f100010 sig=0x0e000010 prob=0.00182147704 name=DEC_fetch_oper_coproc_inst_mcr_ ! mask=0x0f100010 sig=0x0e100010 prob=0.00182147704 name=DEC_fetch_oper_coproc_inst_mrc_ ! mask=0x0e100000 sig=0x0c000000 prob=0.00182147704 name=DEC_fetch_oper_coproc_inst_stc_ mask=0x0ff00000 sig=0x02a00000 prob=0.00182147704 name=DEC_fetch_oper_dpi_imm_binop_adc_ mask=0x0ff00000 sig=0x02b00000 prob=0.00182147704 name=DEC_fetch_oper_dpi_imm_binop_adcs_ *************** *** 1165,1171 **** mask=0x0ff000f0 sig=0x01e00070 prob=0.00182147704 name=DEC_fetch_oper_dpi_rshift_unop_r_ror_mvn_ mask=0x0ff000f0 sig=0x01f00070 prob=0.00182147704 name=DEC_fetch_oper_dpi_rshift_unop_r_ror_mvns_ - mask=0x0f000000 sig=0x0c000000 prob=0.00182147704 name=DEC_fetch_oper_fpe_ - mask=0x0f000000 sig=0x0e000000 prob=0.00182147704 name=DEC_fetch_oper_fpe_ - mask=0x0f100e00 sig=0x0d100e00 prob=0.00182147704 name=DEC_fetch_oper_coproc_ld_ mask=0x0e300000 sig=0x08100000 prob=0.00182147704 name=DEC_fetch_oper_ldm_noupdate_rn_ mask=0x0e300000 sig=0x08300000 prob=0.00182147704 name=DEC_fetch_oper_ldm_update_rn_ --- 1163,1166 ---- *************** *** 1829,1880 **** _FUNC_NAME(DEC_fetch_oper_branch_link_), _FUNC_NAME(DEC_fetch_oper_branch_link_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _STUB_NAME(stub_0_208), ! _STUB_NAME(stub_0_209), ! _STUB_NAME(stub_0_210), ! _STUB_NAME(stub_0_211), ! _STUB_NAME(stub_0_212), ! _STUB_NAME(stub_0_213), ! _STUB_NAME(stub_0_214), ! _STUB_NAME(stub_0_215), ! _STUB_NAME(stub_0_216), ! _STUB_NAME(stub_0_217), ! _STUB_NAME(stub_0_218), ! _STUB_NAME(stub_0_219), ! _STUB_NAME(stub_0_220), ! _STUB_NAME(stub_0_221), ! _STUB_NAME(stub_0_222), ! _STUB_NAME(stub_0_223), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), _FUNC_NAME(DEC_fetch_oper_syscall_), _FUNC_NAME(DEC_fetch_oper_syscall_), --- 1824,1875 ---- _FUNC_NAME(DEC_fetch_oper_branch_link_), _FUNC_NAME(DEC_fetch_oper_branch_link_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _STUB_NAME(stub_0_224), ! _STUB_NAME(stub_0_225), ! _STUB_NAME(stub_0_226), ! _STUB_NAME(stub_0_227), ! _STUB_NAME(stub_0_228), ! _STUB_NAME(stub_0_229), ! _STUB_NAME(stub_0_230), ! _STUB_NAME(stub_0_231), ! _STUB_NAME(stub_0_232), ! _STUB_NAME(stub_0_233), ! _STUB_NAME(stub_0_234), ! _STUB_NAME(stub_0_235), ! _STUB_NAME(stub_0_236), ! _STUB_NAME(stub_0_237), ! _STUB_NAME(stub_0_238), ! _STUB_NAME(stub_0_239), _FUNC_NAME(DEC_fetch_oper_syscall_), _FUNC_NAME(DEC_fetch_oper_syscall_), *************** *** 5522,5666 **** } ! _STUB_ENTRY(stub_0_208) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_209) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_210) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_211) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_212) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_213) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_214) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_215) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_216) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_217) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_218) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_219) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_220) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_221) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_222) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_223) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } --- 5517,5661 ---- } ! _STUB_ENTRY(stub_0_224) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_225) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_226) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_227) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_228) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_229) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_230) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_231) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_232) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_233) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_234) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_235) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_236) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_237) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_238) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_239) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } Index: main.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/main.cpp,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** main.cpp 20 May 2005 06:11:27 -0000 1.4 --- main.cpp 19 Aug 2005 03:15:05 -0000 1.5 *************** *** 59,63 **** if(strcmp(argv[i], "-v") == 0) verbose = true; else if(strcmp(argv[i], "-f") == 0) fpe_name = argv[++i]; else ! if(strcmp(argv[i], "-nf") == 0) need_fpe = false; if(strcmp(argv[i], "-m") == 0) max_cnum = ato_uint64(argv[++i]); else if(strcmp(argv[i], "-h") == 0) {usage(argv[0]); return 0;} else --- 59,63 ---- if(strcmp(argv[i], "-v") == 0) verbose = true; else if(strcmp(argv[i], "-f") == 0) fpe_name = argv[++i]; else ! if(strcmp(argv[i], "-nf") == 0) need_fpe = false; else if(strcmp(argv[i], "-m") == 0) max_cnum = ato_uint64(argv[++i]); else if(strcmp(argv[i], "-h") == 0) {usage(argv[0]); return 0;} else Index: machines.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/machines.cpp,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** machines.cpp 2 Feb 2005 17:53:34 -0000 1.5 --- machines.cpp 19 Aug 2005 03:15:05 -0000 1.6 *************** *** 118,128 **** #define V_syscall_coding C_3 #define V_syscall_imm C_28 ! #define V_fpe_syn C_14 ! #define V_fpe_coding C_5 ! #define V_fpe_pc C_3 ! #define V_coproc_ld_coding C_3 ! #define V_coproc_ld_has_addr C_10 ! #define V_coproc_st_coding C_3 ! #define V_coproc_st_has_addr C_10 #define V_and_coding C_29 #define V_eor_coding C_29 --- 118,122 ---- #define V_syscall_coding C_3 #define V_syscall_imm C_28 ! #define V_coproc_inst_coding C_3 #define V_and_coding C_29 #define V_eor_coding C_29 *************** *** 233,236 **** --- 227,248 ---- #define V_umlals_coding C_12 #define V_umlals_result C_35 + #define V_cdp_coding C_5 + #define V_cdp_cp_num C_1 + #define V_cdp_opcd1 C_9 + #define V_cdp_opcd2 C_12 + #define V_mcr_coding C_5 + #define V_mcr_cp_num C_1 + #define V_mcr_opcd1 C_12 + #define V_mcr_opcd2 C_36 + #define V_mrc_coding C_5 + #define V_mrc_cp_num C_1 + #define V_mrc_opcd1 C_12 + #define V_mrc_opcd2 C_36 + #define V_ldc_coding C_5 + #define V_ldc_offset C_2 + #define V_ldc_cp_num C_1 + #define V_stc_coding C_5 + #define V_stc_offset C_2 + #define V_stc_cp_num C_1 _MACH_CLASS(fetch_normal)::_MACH_CLASS(fetch_normal)(_SIMULATOR *sim):_BASE_MACHINE(sim, 1) { *************** *** 261,264 **** --- 273,277 ---- B_dst15 = NULL; B_cp_buffer = NULL; + B_sc_buffer = NULL; #endif *************** *** 9208,9232 **** } void _MACH_CLASS(fetch_normal)::__dec_544() { ! V_fpe_coding = _temp_coding; ! _MVR(G_cond) = _UINT_XTR2(V_fpe_coding, 31, 28); ! _DIRTY_E_FUN_REF(fpe_syntax, V_fpe_syn, V_fpe_coding); _state_ = L_$S_ID$38080; } void _MACH_CLASS(fetch_normal)::__dec_545() { ! V_coproc_ld_coding = _temp_coding; ! _MVR(G_cond) = _UINT_XTR2(V_coproc_ld_coding, 31, 28); ! V_coproc_ld_has_addr = _UINT_XTR1(V_coproc_ld_coding, 8); _state_ = L_$S_ID$38150; } void _MACH_CLASS(fetch_normal)::__dec_546() { ! V_coproc_st_coding = _temp_coding; ! _MVR(G_cond) = _UINT_XTR2(V_coproc_st_coding, 31, 28); ! V_coproc_st_has_addr = _UINT_XTR1(V_coproc_st_coding, 8); _state_ = L_$S_ID$38220; } void _MACH_CLASS(fetch_normal)::__dec_547() { _state_ = L_$S_ID$38290; } typedef void (_MACH_CLASS(fetch_normal)::*__DECODE_FTYPE)(); static const __DECODE_FTYPE __decs[] = { --- 9221,9287 ---- } void _MACH_CLASS(fetch_normal)::__dec_544() { ! V_coproc_inst_coding = _temp_coding; ! V_cdp_coding = _UINT_XTR2(V_coproc_inst_coding, 31, 0); ! _MVR(G_cond) = _UINT_XTR2(V_cdp_coding, 31, 28); ! V_cdp_opcd1 = _UINT_XTR2(V_cdp_coding, 23, 20); ! _MVR(G_rn) = _UINT_XTR2(V_cdp_coding, 19, 16); ! _MVR(G_rd) = _UINT_XTR2(V_cdp_coding, 15, 12); ! V_cdp_cp_num = _UINT_XTR2(V_cdp_coding, 11, 8); ! V_cdp_opcd2 = _UINT_XTR2(V_cdp_coding, 7, 5); ! _MVR(G_rm) = _UINT_XTR2(V_cdp_coding, 3, 0); _state_ = L_$S_ID$38080; } void _MACH_CLASS(fetch_normal)::__dec_545() { ! V_coproc_inst_coding = _temp_coding; ! V_mcr_coding = _UINT_XTR2(V_coproc_inst_coding, 31, 0); ! _MVR(G_cond) = _UINT_XTR2(V_mcr_coding, 31, 28); ! V_mcr_opcd1 = _UINT_XTR2(V_mcr_coding, 23, 21); ! _MVR(G_rn) = _UINT_XTR2(V_mcr_coding, 19, 16); ! _MVR(G_rd) = _UINT_XTR2(V_mcr_coding, 15, 12); ! V_mcr_cp_num = _UINT_XTR2(V_mcr_coding, 11, 8); ! V_mcr_opcd2 = _UINT_XTR2(V_mcr_coding, 7, 5); ! _MVR(G_rm) = _UINT_XTR2(V_mcr_coding, 3, 0); ! _state_ = L_$S_ID$38150; } void _MACH_CLASS(fetch_normal)::__dec_546() { ! V_coproc_inst_coding = _temp_coding; ! V_mrc_coding = _UINT_XTR2(V_coproc_inst_coding, 31, 0); ! _MVR(G_cond) = _UINT_XTR2(V_mrc_coding, 31, 28); ! V_mrc_opcd1 = _UINT_XTR2(V_mrc_coding, 23, 21); ! _MVR(G_rn) = _UINT_XTR2(V_mrc_coding, 19, 16); ! _MVR(G_rd) = _UINT_XTR2(V_mrc_coding, 15, 12); ! V_mrc_cp_num = _UINT_XTR2(V_mrc_coding, 11, 8); ! V_mrc_opcd2 = _UINT_XTR2(V_mrc_coding, 7, 5); ! _MVR(G_rm) = _UINT_XTR2(V_mrc_coding, 3, 0); ! _state_ = L_$S_ID$38220; } void _MACH_CLASS(fetch_normal)::__dec_547() { + V_coproc_inst_coding = _temp_coding; + V_ldc_coding = _UINT_XTR2(V_coproc_inst_coding, 31, 0); + _MVR(G_cond) = _UINT_XTR2(V_ldc_coding, 31, 28); + _MVR(G_rn) = _UINT_XTR2(V_ldc_coding, 19, 16); + _MVR(G_rd) = _UINT_XTR2(V_ldc_coding, 15, 12); + V_ldc_cp_num = _UINT_XTR2(V_ldc_coding, 11, 8); + V_ldc_offset = _UINT_XTR2(V_ldc_coding, 7, 0); + _state_ = L_$S_ID$38290; } + void _MACH_CLASS(fetch_normal)::__dec_548() { + V_coproc_inst_coding = _temp_coding; + V_stc_coding = _UINT_XTR2(V_coproc_inst_coding, 31, 0); + _MVR(G_cond) = _UINT_XTR2(V_stc_coding, 31, 28); + _MVR(G_rn) = _UINT_XTR2(V_stc_coding, 19, 16); + _MVR(G_rd) = _UINT_XTR2(V_stc_coding, 15, 12); + V_stc_cp_num = _UINT_XTR2(V_stc_coding, 11, 8); + V_stc_offset = _UINT_XTR2(V_stc_coding, 7, 0); + + _state_ = L_$S_ID$38360; + } + void _MACH_CLASS(fetch_normal)::__dec_549() { + _state_ = L_$S_ID$38430; + } typedef void (_MACH_CLASS(fetch_normal)::*__DECODE_FTYPE)(); static const __DECODE_FTYPE __decs[] = { *************** *** 9779,9782 **** --- 9834,9839 ---- &_MACH_CLASS(fetch_normal)::__dec_546, &_MACH_CLASS(fetch_normal)::__dec_547, + &_MACH_CLASS(fetch_normal)::__dec_548, + &_MACH_CLASS(fetch_normal)::__dec_549, }; *************** *** 29344,29348 **** if (!_TEST_ALLOCATE(mEX)) return false; if (!_TEST_INQUIRE(mCPSR)) return false; - if (!_TEST_RELEASE(B_id_buffer)) return false; _BUF(B_ex_buffer) = _ALLOCATE(mEX); --- 29401,29404 ---- *************** *** 29356,29361 **** _FUN_REF(F_eval_pred, _MVR(G_pred), _MVR(G_cond), _MVR(G_v_iflag)); - _RELEASE(B_id_buffer); - return true; } --- 29412,29415 ---- *************** *** 29370,29377 **** bool _MACH_CLASS(fetch_normal)::L_$e_bf_wb$38058() { if (!_TEST_ALLOCATE(mWB)) return false; ! _BUF(B_wb_buffer) = _ALLOCATE(mWB); ! _DIRTY_E_FUN_REF(sys_call, _U2U(24,32,V_syscall_imm)); return true; --- 29424,29432 ---- bool _MACH_CLASS(fetch_normal)::L_$e_bf_wb$38058() { + if (!_TEST_ALLOCATE_ID(mSC, V_syscall_imm)) return false; if (!_TEST_ALLOCATE(mWB)) return false; ! _BUF(B_sc_buffer) = _ALLOCATE_ID(mSC, V_syscall_imm); ! _BUF(B_wb_buffer) = _ALLOCATE(mWB); return true; *************** *** 29379,29385 **** --- 29434,29444 ---- bool _MACH_CLASS(fetch_normal)::L_$e_wb_in$38076() { + if (!_TEST_RELEASE(B_id_buffer)) return false; if (!_TEST_RELEASE(B_ex_buffer)) return false; if (!_TEST_RELEASE(B_bf_buffer)) return false; if (!_TEST_RELEASE(B_wb_buffer)) return false; + if (!_TEST_RELEASE(B_sc_buffer)) return false; + _RELEASE(B_id_buffer); + _RELEASE(B_ex_buffer); *************** *** 29388,29391 **** --- 29447,29452 ---- _RELEASE(B_wb_buffer); + _RELEASE(B_sc_buffer); + return true; } *************** *** 29393,29409 **** bool _MACH_CLASS(fetch_normal)::L_$e_id_ex$38105() { if (!_TEST_ALLOCATE(mEX)) return false; - if (!_TEST_INQUIRE_ID(mRF, _UINT_CTR(4, 0xf))) return false; if (!_TEST_INQUIRE(mCPSR)) return false; - if (!_TEST_RELEASE(B_id_buffer)) return false; _BUF(B_ex_buffer) = _ALLOCATE(mEX); { - _UINT_T(32) L_temp; - _READ_TOKEN_ID(L_temp,mRF, _UINT_CTR(4, 0xf)); - V_fpe_pc = L_temp; - } - - - { _UINT_T(4) L_temp; _READ_TOKEN(L_temp,mCPSR); --- 29454,29461 ---- *************** *** 29414,29474 **** _FUN_REF(F_eval_pred, _MVR(G_pred), _MVR(G_cond), _MVR(G_v_iflag)); - _RELEASE(B_id_buffer); - return true; } bool _MACH_CLASS(fetch_normal)::L_$e_bf_wb$38128() { if (!_TEST_ALLOCATE(mWB)) return false; ! if (!(_TEST_ALLOCATE(mReset))) return false; ! _BUF(B_wb_buffer) = _ALLOCATE(mWB); ! ! _DIRTY_E_FUN_REF(fpe_emul, _MVR(G_iw), V_fpe_pc); ! ! { ! _WRITE_TOKEN(mReset, _TUPLE_CTR(_UINT_T(4), _UINT_T(1), _UINT_CTR(4, 0xf), _UINT_CTR(1, 0x1))); ! } return true; } ! bool _MACH_CLASS(fetch_normal)::L_$e_id_ex$38175() { ! if (!_TEST_ALLOCATE(mEX)) return false; ! if (!_TEST_INQUIRE(mCPSR)) return false; if (!_TEST_RELEASE(B_id_buffer)) return false; - _BUF(B_ex_buffer) = _ALLOCATE(mEX); - - { - _UINT_T(4) L_temp; - _READ_TOKEN(L_temp,mCPSR); - _MVR(G_v_iflag) = L_temp; - } - - - _FUN_REF(F_eval_pred, _MVR(G_pred), _MVR(G_cond), _MVR(G_v_iflag)); - - _RELEASE(B_id_buffer); - - return true; - } - - bool _MACH_CLASS(fetch_normal)::L_$e_ex_bf$38179() { - if (!_COMPARE(_MVR(G_pred), >, _UINT_CTR(1, 0x0))) return false; - if (!_TEST_ALLOCATE_ID(mCoProc, _TUPLE_CTR(_UINT_T(1), _UINT_T(1), _UINT_CTR(1, 0x0), V_coproc_ld_has_addr))) return false; - if (!_TEST_ALLOCATE(mBF)) return false; - _BUF(B_cp_buffer) = _ALLOCATE_ID(mCoProc, _TUPLE_CTR(_UINT_T(1), _UINT_T(1), _UINT_CTR(1, 0x0), V_coproc_ld_has_addr)); - - _BUF(B_bf_buffer) = _ALLOCATE(mBF); - - return true; - } - - bool _MACH_CLASS(fetch_normal)::L_$e_bf_wb$38198() { - if (!_TEST_ALLOCATE(mWB)) return false; i... [truncated message content] |
|
From: Wei Q. <wei...@us...> - 2005-05-21 20:28:57
|
Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv22432/simulator Modified Files: cache.h Log Message: renamed some cache functions Index: cache.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/cache.h,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** cache.h 12 Nov 2004 06:40:32 -0000 1.3 --- cache.h 21 May 2005 20:28:48 -0000 1.4 *************** *** 19,31 **** protected: ! uint32_t cache_index(uint32_t addr) { return (addr/bsize)%(n_block/n_assoc); } ! uint32_t cache_tag(uint32_t addr) { return (addr/(bsize*n_block/n_assoc)); } ! /* ARM uses the round robin policy */ uint32_t choose_round_robin(uint32_t index) { return round_robin_index[index]; --- 19,35 ---- protected: ! uint32_t get_index(uint32_t addr) { return (addr/bsize)%(n_block/n_assoc); } ! uint32_t get_tag(uint32_t addr) { return (addr/(bsize*n_block/n_assoc)); } ! uint32_t get_address(uint32_t index, uint32_t tag) { ! return (tag*(n_block/n_assoc) + index)*bsize; ! } ! ! /* StrongARM uses the round robin policy */ uint32_t choose_round_robin(uint32_t index) { return round_robin_index[index]; *************** *** 37,42 **** /* check if the address is in cache */ ! struct cache_block *lookup(uint32_t addr) { ! uint32_t ind = cache_index(addr), tag = cache_tag(addr); for (uint32_t i=0; i<n_assoc; i++) if (data[ind][i].tag == tag && data[ind][i].valid) --- 41,46 ---- /* check if the address is in cache */ ! struct cache_block *look_up(uint32_t addr) { ! uint32_t ind = get_index(addr), tag = get_tag(addr); for (uint32_t i=0; i<n_assoc; i++) if (data[ind][i].tag == tag && data[ind][i].valid) *************** *** 46,52 **** /* allocate a cache block, return true if eviction happened */ ! struct cache_block *allocateBlock(uint32_t addr, uint32_t size) { ! uint32_t ind = cache_index(addr), tag = cache_tag(addr); cache_block *theblock = &data[ind][choose_round_robin(ind)]; --- 50,56 ---- /* allocate a cache block, return true if eviction happened */ ! struct cache_block *allocate_block(uint32_t addr, uint32_t size) { ! uint32_t ind = get_index(addr), tag = get_tag(addr); cache_block *theblock = &data[ind][choose_round_robin(ind)]; *************** *** 79,85 **** using base_t::name; using base_t::data; ! using base_t::round_robin_index; ! using base_t::lookup; ! using base_t::allocateBlock; public: --- 83,88 ---- using base_t::name; using base_t::data; ! using base_t::look_up; ! using base_t::allocate_block; public: *************** *** 114,118 **** } ! struct cache_block *block = lookup(addr); if (!block) { nReadMisses++; --- 117,121 ---- } ! struct cache_block *block = look_up(addr); if (!block) { nReadMisses++; *************** *** 121,125 **** /* read the block in */ latency = biu.access(r_latency); ! block = allocateBlock(addr, size); return false; --- 124,128 ---- /* read the block in */ latency = biu.access(r_latency); ! block = allocate_block(addr, size); return false; *************** *** 165,170 **** using base_t::data; using base_t::round_robin_index; ! using base_t::lookup; ! using base_t::allocateBlock; private: --- 168,173 ---- using base_t::data; using base_t::round_robin_index; ! using base_t::look_up; ! using base_t::allocate_block; private: *************** *** 222,226 **** if (read_busy) return false; ! struct cache_block *block = lookup(addr); if (!block) { nReadMisses++; --- 225,229 ---- if (read_busy) return false; ! struct cache_block *block = look_up(addr); if (!block) { nReadMisses++; *************** *** 229,233 **** /* read the block in */ latency = biu.access(r_latency); ! block = allocateBlock(addr, size); /* add eviction cost if dirty*/ --- 232,236 ---- /* read the block in */ latency = biu.access(r_latency); ! block = allocate_block(addr, size); /* add eviction cost if dirty*/ *************** *** 255,259 **** //if (write_busy) return false; ! struct cache_block *block = lookup(addr); /* cache hit, good */ if (block) { --- 258,262 ---- //if (write_busy) return false; ! struct cache_block *block = look_up(addr); /* cache hit, good */ if (block) { |
|
From: Wei Q. <wei...@us...> - 2005-05-21 20:28:56
|
Update of /cvsroot/simit-arm/simit-arm In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv22432 Modified Files: ChangeLog Log Message: renamed some cache functions Index: ChangeLog =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/ChangeLog,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** ChangeLog 20 May 2005 06:11:26 -0000 1.5 --- ChangeLog 21 May 2005 20:28:48 -0000 1.6 *************** *** 79,83 **** somewhere in the library. Change that to dg_label_t. ! SimIt-ARM-2.2 1. Removed emu_single, reverted related changes in version 2.1. Too complicated and not worthwhile the slight performance gain. --- 79,83 ---- somewhere in the library. Change that to dg_label_t. ! SimIt-ARM-2.1.1,5-21-2005, cleanup not really to be released 1. Removed emu_single, reverted related changes in version 2.1. Too complicated and not worthwhile the slight performance gain. |
|
From: Wei Q. <wei...@us...> - 2005-05-21 20:28:56
|
Update of /cvsroot/simit-arm/simit-arm/emulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv22432/emulator Modified Files: loadfpe.cpp Log Message: renamed some cache functions Index: loadfpe.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/loadfpe.cpp,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** loadfpe.cpp 20 May 2005 06:11:27 -0000 1.4 --- loadfpe.cpp 21 May 2005 20:28:48 -0000 1.5 *************** *** 13,16 **** --- 13,19 ---- #include <cstring> + using emulator::MEMORY_PAGE_READABLE; + using emulator::MEMORY_PAGE_EXECUTABLE; + void armulator::load_fpe(const char *fname) { *************** *** 98,103 **** if (new_section_flags&SHF_EXECINSTR) { #ifdef EMUMEM_SAFE ! // mem->set_permission(new_section_addr, new_section_size, ! // MEMORY_PAGE_READABLE | MEMORY_PAGE_EXECUTABLE); if (verbose) --- 101,106 ---- if (new_section_flags&SHF_EXECINSTR) { #ifdef EMUMEM_SAFE ! mem->set_permission(new_section_addr, new_section_size, ! MEMORY_PAGE_READABLE | MEMORY_PAGE_EXECUTABLE); if (verbose) |
|
From: Wei Q. <wei...@us...> - 2005-05-20 06:11:39
|
Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv17311/simulator Modified Files: Makefile.am armsim.cpp armsim.hpp ext_func.cpp main.cpp Log Message: massive update, see changelog for details Index: main.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/main.cpp,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** main.cpp 2 Feb 2005 17:53:34 -0000 1.3 --- main.cpp 20 May 2005 06:11:27 -0000 1.4 *************** *** 21,28 **** "**** " PACKAGE " Version " VERSION " (C) 2002,2003,2004,2005 Wei Qin ****\n" ! "usage : %s [-v] [-m maxcycle] [-f fpe-path] [-h] <file name> <args...>\n" " -v : verbose\n" " -m : maximum number of cycles to simulate\n" " -f : FPE binary file path\n" " -h : print this message\n" " file name : the ARM ELF32 program to simulate\n" --- 21,29 ---- "**** " PACKAGE " Version " VERSION " (C) 2002,2003,2004,2005 Wei Qin ****\n" ! "usage : %s [-v] [-m maxcycle] [-f fpe-path] [-nf] [-h] <file name> <args...>\n" " -v : verbose\n" " -m : maximum number of cycles to simulate\n" " -f : FPE binary file path\n" + " -nf: no fpe needed\n" " -h : print this message\n" " file name : the ARM ELF32 program to simulate\n" *************** *** 30,43 **** } ! arm_simulator *sima; ! ! void sigint_handler(int signum) { ! if (sima->is_running()) { ! sima->stop(); } ! else { ! delete sima; ! exit(0); } } --- 31,45 ---- } ! static arm_simulator *sima; ! static void sig_handler(int signum) { ! /* do nothing if the simulator does not exist */ ! if (sima==NULL) exit(0); ! ! if (signum==SIGINT) { ! sima->interrupt(); } ! else if (signum==SIGUSR1) { ! sima->seg_fault(); } } *************** *** 49,54 **** char *fpe_name = NULL; bool verbose = false; uint64_t max_cnum = (uint64_t)-1; ! void (*prev_sigint_handler)(int); for(i = 1; i < argc; i++) --- 51,57 ---- char *fpe_name = NULL; bool verbose = false; + bool need_fpe = true; uint64_t max_cnum = (uint64_t)-1; ! void (*prev_sig_handler)(int); for(i = 1; i < argc; i++) *************** *** 56,59 **** --- 59,63 ---- if(strcmp(argv[i], "-v") == 0) verbose = true; else if(strcmp(argv[i], "-f") == 0) fpe_name = argv[++i]; else + if(strcmp(argv[i], "-nf") == 0) need_fpe = false; if(strcmp(argv[i], "-m") == 0) max_cnum = ato_uint64(argv[++i]); else if(strcmp(argv[i], "-h") == 0) {usage(argv[0]); return 0;} else *************** *** 68,75 **** if(prog_name) { ! sima = new arm_simulator(verbose); ! prev_sigint_handler = signal(SIGINT, sigint_handler); ! sima->load_fpe(fpe_name); sima->load_program(prog_name, argc - i, argv + i, envp); --- 72,82 ---- if(prog_name) { ! sima = new arm_simulator(verbose, need_fpe, true); ! signal(SIGUSR1, sig_handler); ! prev_sig_handler = signal(SIGINT, sig_handler); ! ! if (need_fpe) ! sima->load_fpe(fpe_name); sima->load_program(prog_name, argc - i, argv + i, envp); *************** *** 84,88 **** sima->run(max_cnum); - if(prev_sigint_handler != SIG_ERR) signal(SIGINT, SIG_DFL); sima->dump_stats(stderr); --- 91,94 ---- *************** *** 103,108 **** #endif ! delete sima; } else usage(argv[0]); --- 109,116 ---- #endif ! if(prev_sig_handler != SIG_ERR) signal(SIGINT, SIG_DFL); ! signal(SIGUSR1, SIG_IGN); + delete sima; } else usage(argv[0]); Index: ext_func.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/ext_func.cpp,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** ext_func.cpp 12 Nov 2004 06:33:01 -0000 1.2 --- ext_func.cpp 20 May 2005 06:11:27 -0000 1.3 *************** *** 43,47 **** static void disasm_ldstm(arm_simulator *sm, arm_inst_t inst, ostream& strm) { ! UInt32 i, first = 1; strm << (LFLD?"ldm":"stm") << cond_names[COND] --- 43,47 ---- static void disasm_ldstm(arm_simulator *sm, arm_inst_t inst, ostream& strm) { ! uint32_t i, first = 1; strm << (LFLD?"ldm":"stm") << cond_names[COND] Index: armsim.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.cpp,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** armsim.cpp 3 Apr 2005 19:47:30 -0000 1.4 --- armsim.cpp 20 May 2005 06:11:27 -0000 1.5 *************** *** 24,30 **** using std::list; ! arm_simulator::arm_simulator(bool verbose) : ! running(false), debuging(false), verbose(verbose), in_fpe(false), mem() { /* create the hardware modules */ biu = new BIU("biu"); --- 24,31 ---- using std::list; ! arm_simulator::arm_simulator(bool verbose, bool need_fpe, bool emu_syscall) : ! verbose(verbose), need_fpe(need_fpe), emu_syscall(emu_syscall) { + /* create the hardware modules */ biu = new BIU("biu"); *************** *** 98,101 **** --- 99,103 ---- reset_stats(); + status = ST_RESET; in_fpe = false; } *************** *** 135,138 **** --- 137,166 ---- } + void arm_simulator::prog_exit(int ret) + { + status = ST_EXIT; + retcode = ret; + } + + void arm_simulator::interrupt() + { + if (status==ST_RUNNING || status==ST_DEBUGGING) + status = ST_SIGINT; + else + exit(0); + } + + void arm_simulator::break_point() + { + if (status==ST_RUNNING || status==ST_DEBUGGING) + status = ST_BREAK; + } + + void arm_simulator::seg_fault() + { + status = ST_ERROR; + retcode = 1; + } + void arm_simulator::clock_tick() *************** *** 187,201 **** } ! void arm_simulator::initialize() { _opt_machine_ *src = source_machine(); work_list.push_back(src); ! running = true; ! } ! void arm_simulator::run(UInt64 maxCycle) ! { ! initialize(); ! while(running && cycle_count<=maxCycle) { clock_tick(); } --- 215,226 ---- } ! ! void arm_simulator::run(uint64_t maxCycle) { _opt_machine_ *src = source_machine(); work_list.push_back(src); ! status = ST_RUNNING; ! while(status==ST_RUNNING && cycle_count<=maxCycle) { clock_tick(); } Index: Makefile.am =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/Makefile.am,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** Makefile.am 1 Mar 2005 07:20:49 -0000 1.2 --- Makefile.am 20 May 2005 06:11:27 -0000 1.3 *************** *** 2,33 **** bin_PROGRAMS = sima ! sima_SOURCES = define.cpp fetch_oper_pat.hpp machines.cpp \ ! fetch_oper_tab.hpp main.cpp armsim.cpp \ ! func.hpp more_managers.cpp \ ! ext_func.cpp \ ! fetch_oper_dec.cpp \ ! BIU.h machines.hpp parms.h \ ! cache.h fetch_oper_dec.hpp mach_list.hpp \ ! mang_list.hpp armsim.hpp \ ! define.hpp include_osm.hpp \ ! include_temp.hpp more_managers.hpp interface.hpp ! ! sima_LDADD = syscall.o loadfpe.o loader.o nwfpe.o \ ! $(top_builddir)/emulator/emumem.o $(top_builddir)/emulator/read_elf.o \ ! $(top_builddir)/emulator/util.o $(top_builddir)/emulator/emu_device.o \ ! $(top_builddir)/emulator/external_dev_stub.o \ ! $(top_builddir)/emulator/external_mem_stub.o ! ! syscall.o: $(top_srcdir)/emulator/syscall.cpp ! $(CXXCOMPILE) -c $< -o $@ ! ! loadfpe.o: $(top_srcdir)/emulator/loadfpe.cpp ! $(CXXCOMPILE) -c $< -o $@ ! ! loader.o: $(top_srcdir)/emulator/loader.cpp ! $(CXXCOMPILE) -c $< -o $@ ! nwfpe.o: $(top_srcdir)/emulator/nwfpe.cpp ! $(CXXCOMPILE) -c $< -o $@ AM_CPPFLAGS = -D__COMPILE_SIMULATOR_ --- 2,8 ---- bin_PROGRAMS = sima ! sima_SOURCES = main.cpp ! sima_LDADD = libarmsim.a AM_CPPFLAGS = -D__COMPILE_SIMULATOR_ *************** *** 39,62 **** lib_LIBRARIES = libarmsim.a ! libarmsim_a_SOURCES = define.cpp fetch_oper_pat.hpp machines.cpp \ ! fetch_oper_tab.hpp armsim.cpp \ ! func.hpp more_managers.cpp \ ! ext_func.cpp \ ! fetch_oper_dec.cpp \ ! BIU.h machines.hpp parms.h \ ! cache.h fetch_oper_dec.hpp mach_list.hpp \ mang_list.hpp armsim.hpp \ define.hpp include_osm.hpp \ ! include_temp.hpp more_managers.hpp \ ! interface.hpp ! libarmsim_a_LIBADD = syscall.o loadfpe.o loader.o nwfpe.o \ $(top_builddir)/emulator/emumem.o $(top_builddir)/emulator/read_elf.o \ $(top_builddir)/emulator/util.o $(top_builddir)/emulator/emu_device.o \ ! $(top_builddir)/emulator/external_dev_stub.o \ ! $(top_builddir)/emulator/external_mem_stub.o ! include_HEADERS = BIU.h parms.h \ ! cache.h mach_list.hpp mang_list.hpp armsim.hpp \ ! define.hpp include_osm.hpp \ ! more_managers.hpp --- 14,37 ---- lib_LIBRARIES = libarmsim.a ! libarmsim_a_SOURCES = define.cpp machines.cpp \ ! main.cpp armsim.cpp more_managers.cpp \ ! ext_func.cpp fetch_oper_dec.cpp \ mang_list.hpp armsim.hpp \ define.hpp include_osm.hpp \ ! include_temp.hpp more_managers.hpp interface.hpp \ ! cache.h fetch_oper_dec.hpp mach_list.hpp \ ! BIU.h machines.hpp parms.h \ ! fetch_oper_pat.hpp fetch_oper_tab.hpp func.hpp \ ! $(top_builddir)/emulator/syscall.cpp \ ! $(top_builddir)/emulator/loadfpe.cpp \ ! $(top_builddir)/emulator/loader.cpp \ ! $(top_builddir)/emulator/nwfpe.cpp ! libarmsim_a_LIBADD = \ $(top_builddir)/emulator/emumem.o $(top_builddir)/emulator/read_elf.o \ $(top_builddir)/emulator/util.o $(top_builddir)/emulator/emu_device.o \ ! $(top_builddir)/emulator/external_dev_stub.o ! include_HEADERS = parms.h more_managers.hpp \ ! include_osm.hpp cache.h BIU.h armsim.hpp \ ! mach_list.hpp mang_list.hpp Index: armsim.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.hpp,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** armsim.hpp 12 Nov 2004 06:33:01 -0000 1.2 --- armsim.hpp 20 May 2005 06:11:27 -0000 1.3 *************** *** 21,27 **** typedef class rcache<nICacheBlocks, nICacheAssoc, ! ICacheLineSize, memoryReadLatency> ICache; typedef class rwcache<nDCacheBlocks, nDCacheAssoc, ! DCacheLineSize, memoryReadLatency, memoryWriteLatency> DCache; typedef class rcache<nITLBBlocks, nITLBAssoc, IPageSize, tlbLoadLatency> ITLB; typedef class rcache<nDTLBBlocks, nDTLBAssoc, DPageSize, tlbLoadLatency> DTLB; --- 21,27 ---- typedef class rcache<nICacheBlocks, nICacheAssoc, ! ICacheLineSize, memoryReadLatency> ICache; typedef class rwcache<nDCacheBlocks, nDCacheAssoc, ! DCacheLineSize, memoryReadLatency, memoryWriteLatency> DCache; typedef class rcache<nITLBBlocks, nITLBAssoc, IPageSize, tlbLoadLatency> ITLB; typedef class rcache<nDTLBBlocks, nDTLBAssoc, DPageSize, tlbLoadLatency> DTLB; *************** *** 30,199 **** class device_emulator; ! class arm_simulator { enum _machine_id { _mach_dummy, ! #define _MACH_DEF(_a,_b) _mach_ ## _b, ! #include "mach_list.hpp" _mach_total, }; ! public: ! /** Constructor. ! * @param verbose Verbose mode ! */ ! arm_simulator(bool verbose); ! /** Destructor. */ ! ~arm_simulator(); ! /** Initialize the simulation state. ! */ ! void initialize(); ! /** simulate for n cycles. ! * @param n The maximum number of cycles to simulate (may exit). ! */ ! void run(UInt64 n); ! /** simulate one cycle. */ ! void clock_tick(); ! /** stop running. ! * Called by the signal handler or syscall interpreter. ! */ ! void stop() {running = false;} - /** See if the simulator is running. - */ - bool is_running() const {return running;} - /** Stop debuging, useless here. - * Kept only to satisfy syscall.cpp. - */ - void stop_debug() {debuging = false;} - /** See if in debugging mode, useless here. - * Kept only to satisfy syscall.cpp. - */ - bool is_debugging() {return debuging;} ! /** stats output. */ ! void dump_stats(FILE *fp); ! /** stats resetting. */ ! void reset_stats(); ! /* set brk point for syscall interpretation. */ ! void set_brk(arm_addr_t addr) {brk_point = addr;} ! void set_mmap_brk(arm_addr_t addr) {mmap_brk_point = addr;} - /** load the program into memory. */ - void load_program(const char *, int argc, char *argv[], char *env[]); - /** load fpe emulation library into memory. */ - void load_fpe(const char *); - /** reset */ - void reset(); ! /** Get the value of a register. For debugging use. */ ! word_t read_gpr(int ind) const { ! return mRF->get_value(ind).val(); ! } ! /** These two hooks for the syscall interpretor. */ ! void write_gpr(int ind, word_t val) { ! mRF->set_value(ind, val); ! } ! void write_gpr2(int ind, word_t val) { ! mRF->set_value(ind, val); ! } ! uint64_t get_cycle_count() const {return cycle_count;} ! word_t read_cpsr() {return mCPSR->get_value().val();} ! void write_cpsr(word_t val) {mCPSR->set_value(val);} ! #if 0 ! word_t read_spsr() {return my_regs.spsr;} ! void write_spsr(word_t val) {my_regs.spsr=val;} ! #endif - private: - /* status flags */ - bool running; - bool debuging; - uint64_t cycle_count; /* number of simulation cycles*/ - std::list<_opt_machine_ *> work_list; - std::list<_opt_machine_ *>::iterator work_it, ins_it; ! public: ! /* syscall data */ ! bool verbose; ! bool emulate_syscall; ! target_addr_t brk_point; ! target_addr_t mmap_brk_point; ! /* emulating fpe */ ! bool in_fpe; ! public: - uint64_t alloc_count; /* number of machine allocations. */ - uint64_t retire_count; /* number of machine retires. */ - /* Allocate a machine of given id type. */ - _opt_machine_ *allocate_machine(_MACH_ID_T id); - /* This is the sink of OSMs. */ - void sink_machine(_opt_machine_ *mach); ! /* Get a new machine. ! * This is the source of OSMs. ! */ ! _opt_machine_ *source_machine(); ! /** Activate a new machine. ! * @param id The id of the machine. ! */ ! void activate_machine(_MACH_ID_T id); - private: - static _opt_machine_ *mach_allocator(arm_simulator *, _MACH_ID_T id); ! /* storage for machine objects. */ ! obj_pool<_opt_machine_, _MACH_ID_T, arm_simulator, ! arm_simulator::mach_allocator> *machine_pool; ! /*hardware units */ ! public: ! /* caches, TLBs & bus interface unit, modeling timing only */ ! ICache *icache; ! DCache *dcache; ! ITLB *itlb; ! DTLB *dtlb; ! BIU *biu; ! /* the token managers */ #define MANG_DEF(cname, iname) cname *iname; #include "mang_list.hpp" ! emulator::device_master *dev_master; - /* memory saving the real data value */ - emulator::memory *mem; ! }; } --- 30,246 ---- class device_emulator; ! class arm_simulator { enum _machine_id { _mach_dummy, ! #define _MACH_DEF(_a,_b) _mach_ ## _b, ! #include "mach_list.hpp" _mach_total, }; ! enum status_t { ! ST_RESET, // just reset, empty ! ST_IDLE, // program loaded ! ST_RUNNING, ! ST_DEBUGGING, ! ST_ERROR, // memory protection violation ! ST_EXIT, // program exit normally ! ST_SIGINT, // user interrupted ! ST_BREAK, // brk instruction ! }; ! public: ! /** Constructor. ! * @param verbose Verbose mode ! */ ! arm_simulator(bool verbose, bool need_fpe, bool emulate_syscall); ! /** Destructor. */ ! ~arm_simulator(); ! /* reset everything */ ! void reset(); ! /* if verbose flag set */ ! bool is_verbose() const {return verbose;} ! /* if syscall need to be emulated */ ! bool emulate_syscall() const {return emu_syscall;} ! /** load the program into memory. */ ! void load_program(const char *, int argc, char *argv[], char *env[]); ! /** load fpe emulation library into memory. */ ! void load_fpe(const char *); ! /* reload the program, for restarting debugger */ ! void reload(); ! /** simulate for n cycles. ! * @param n The maximum number of cycles to simulate (may exit). ! */ ! void run(uint64_t n); ! /** simulate one cycle. */ ! void clock_tick(); ! /* program exit */ ! void prog_exit(int); ! bool is_done() const {return status==ST_EXIT;} ! /* user interruption */ ! void interrupt(); ! bool is_interrupted() const {return status==ST_SIGINT;} ! /* brk instruction */ ! void break_point(); ! bool is_broken() const {return status==ST_BREAK;} ! /* error */ ! void seg_fault(); ! bool is_fault() const {return status==ST_ERROR;} ! /* check status */ ! bool is_running() const {return status==ST_RUNNING;} ! bool is_debugging() const {return status==ST_DEBUGGING;} + /* get exit code of the program */ + int get_retcode() const {return retcode;} ! /** stats output. */ ! void dump_stats(FILE *fp); ! /** stats resetting. */ ! void reset_stats(); ! /* get the number of cycles */ ! uint64_t get_cycle_count() const {return cycle_count;} ! /* some system-call library variables */ ! arm_addr_t get_brk() const {return brk_point;} ! arm_addr_t get_mmap_brk() const {return mmap_brk_point;} ! /* set brk point for syscall interpretation. */ ! void set_brk(arm_addr_t addr) {brk_point = addr;} ! void set_mmap_brk(arm_addr_t addr) {mmap_brk_point = addr;} ! /** Get the value of a register. For debugging use. */ ! word_t read_gpr(int ind) const { ! return mRF->get_value(ind).val(); ! } ! /** These two hooks for the syscall interpretor. */ ! void write_gpr(int ind, word_t val) { ! mRF->set_value(ind, val); ! } ! void write_gpr2(int ind, word_t val) { ! mRF->set_value(ind, val); ! } ! word_t read_cpsr() {return mCPSR->get_value().val();} ! void write_cpsr(word_t val) {mCPSR->set_value(val);} ! #if 0 ! word_t read_spsr() {return my_regs.spsr;} ! ! void write_spsr(word_t val) {my_regs.spsr=val;} ! #endif ! ! ! /** Activate a new machine. ! * @param id The id of the machine. ! */ ! void activate_machine(_MACH_ID_T id); ! ! ! /* don't know what is this is good for */ ! emulator::device_master *dev_master; ! ! /* memory saving the real data value */ ! emulator::memory *mem; ! ! /* the token managers */ #define MANG_DEF(cname, iname) cname *iname; #include "mang_list.hpp" ! /* emulating fpe */ ! bool in_fpe; ! private: ! ! /* syscall data */ ! bool verbose; ! bool need_fpe; ! bool emu_syscall; ! ! ! int retcode; // valid on ST_EXIT ! ! /* status flags */ ! enum status_t status; ! ! uint64_t cycle_count; /* number of simulation cycles*/ ! ! std::list<_opt_machine_ *> work_list; ! std::list<_opt_machine_ *>::iterator work_it, ins_it; ! ! ! target_addr_t brk_point; ! target_addr_t mmap_brk_point; ! ! uint64_t alloc_count; /* number of machine allocations. */ ! uint64_t retire_count; /* number of machine retires. */ ! ! /* Allocate a machine of given id type. */ ! _opt_machine_ *allocate_machine(_MACH_ID_T id); ! ! /* This is the sink of OSMs. */ ! void sink_machine(_opt_machine_ *mach); ! ! /* Get a new machine. ! * This is the source of OSMs. ! */ ! _opt_machine_ *source_machine(); ! ! static _opt_machine_ *mach_allocator(arm_simulator *, _MACH_ID_T id); ! ! /* storage for machine objects. */ ! obj_pool<_opt_machine_, _MACH_ID_T, arm_simulator, ! arm_simulator::mach_allocator> *machine_pool; ! ! /*hardware units */ ! ! ! /* caches, TLBs & bus interface unit, modeling timing only */ ! ICache *icache; ! DCache *dcache; ! ITLB *itlb; ! DTLB *dtlb; ! BIU *biu; ! ! const char *fpe_cache; ! const char *fname_cache; ! int argc_cache; ! char **argv_cache; ! char **envp_cache; ! }; } |
|
From: Wei Q. <wei...@us...> - 2005-05-20 06:11:37
|
Update of /cvsroot/simit-arm/simit-arm/libosm In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv17311/libosm Modified Files: osm.hpp Log Message: massive update, see changelog for details Index: osm.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/libosm/osm.hpp,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** osm.hpp 12 Nov 2004 06:33:00 -0000 1.2 --- osm.hpp 20 May 2005 06:11:27 -0000 1.3 *************** *** 258,261 **** --- 258,264 ---- /** Constructor. */ + _token_() : _tenant_(NULL), _boss_(NULL) {} + + /** Constructor. */ _token_(_M_ *m) : _tenant_(NULL), _boss_(m) {} |
|
From: Wei Q. <wei...@us...> - 2005-05-20 06:11:37
|
Update of /cvsroot/simit-arm/simit-arm In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv17311 Modified Files: ChangeLog Makefile.am Log Message: massive update, see changelog for details Index: Makefile.am =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/Makefile.am,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** Makefile.am 2 Feb 2005 06:42:05 -0000 1.3 --- Makefile.am 20 May 2005 06:11:26 -0000 1.4 *************** *** 1,4 **** ! SUBDIRS = libosm emulator emu_single simulator decgen EXTRA_DIST = test/grep test/wc \ --- 1,4 ---- ! SUBDIRS = libosm emulator simulator decgen EXTRA_DIST = test/grep test/wc \ Index: ChangeLog =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/ChangeLog,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** ChangeLog 2 Feb 2005 17:10:15 -0000 1.4 --- ChangeLog 20 May 2005 06:11:26 -0000 1.5 *************** *** 78,79 **** --- 78,88 ---- 4. Fixed one portability problem in decgen/decode.h. label_t is used somewhere in the library. Change that to dg_label_t. + + SimIt-ARM-2.2 + 1. Removed emu_single, reverted related changes in version 2.1. + Too complicated and not worthwhile the slight performance gain. + 2. Improved memory emulator, added access permission control. + 4. Remved the original external memory interface since the new memory + emulator has integrated similar function in a better way. + 3. Fixed some bugs in libosm/mpz_base.?pp. The bugs were irrelevant + to SimIt-ARM since this part of the library was not used in SimIt. |
|
From: Wei Q. <wei...@us...> - 2005-04-03 20:24:27
|
Update of /cvsroot/simit-arm/simit-arm/decgen In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv7571/decgen Modified Files: Tag: sc_branch undef.cpp Log Message: improved decoder generation Index: undef.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/decgen/undef.cpp,v retrieving revision 1.2.2.1 retrieving revision 1.2.2.2 diff -C2 -d -r1.2.2.1 -r1.2.2.2 *** undef.cpp 3 Apr 2005 20:09:58 -0000 1.2.2.1 --- undef.cpp 3 Apr 2005 20:24:00 -0000 1.2.2.2 *************** *** 63,65 **** --- 63,66 ---- entries.push_back(pattern2entry(*pat_it)); } + return true; } |
Update of /cvsroot/simit-arm/simit-arm/emulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv7571/emulator Modified Files: Tag: sc_branch Makefile.am arm_dec.h arm_inst_wfpe_nonull.def armemul.cpp armemul.h main.cpp Log Message: improved decoder generation Index: arm_dec.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/arm_dec.h,v retrieving revision 1.2.2.1 retrieving revision 1.2.2.2 diff -C2 -d -r1.2.2.1 -r1.2.2.2 *** arm_dec.h 28 Dec 2004 05:54:24 -0000 1.2.2.1 --- arm_dec.h 3 Apr 2005 20:24:00 -0000 1.2.2.2 *************** *** 1,7 **** /* ! Binary decoder synthesized by SimIt-ARM version 2.0.4 Input statistics ! Total entries : 191 Unique labels : 131 Shannon entropy : 6.99511 --- 1,7 ---- /* ! Binary decoder synthesized by SimIt-ARM-sc version 2.1pre4 [...1931 lines suppressed...] if _PATTERN_TRUE(0x00000f00, 0x00000000) { --- 2223,2227 ---- } ! _STUB_ENTRY(stub_10_13) { if _PATTERN_TRUE(0x00000f00, 0x00000000) { *************** *** 2039,2043 **** } ! _STUB_ENTRY(stub_8_15) { if _PATTERN_TRUE(0x00000f00, 0x00000000) { --- 2232,2236 ---- } ! _STUB_ENTRY(stub_10_15) { if _PATTERN_TRUE(0x00000f00, 0x00000000) { Index: main.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/main.cpp,v retrieving revision 1.2.2.1 retrieving revision 1.2.2.2 diff -C2 -d -r1.2.2.1 -r1.2.2.2 *** main.cpp 2 Feb 2005 18:00:20 -0000 1.2.2.1 --- main.cpp 3 Apr 2005 20:24:00 -0000 1.2.2.2 *************** *** 94,98 **** #endif ! UInt64 icount = ema.run_count(max_inum); #if HAVE_SYS_RESOURCE_H && HAVE_SYS_TIME_H --- 94,102 ---- #endif ! UInt64 icount; ! if (max_inum==(UInt64)-1) ! icount = ema.run(); ! else ! icount = ema.run_count(max_inum); #if HAVE_SYS_RESOURCE_H && HAVE_SYS_TIME_H Index: Makefile.am =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/Makefile.am,v retrieving revision 1.1.1.1.2.1 retrieving revision 1.1.1.1.2.2 diff -C2 -d -r1.1.1.1.2.1 -r1.1.1.1.2.2 *** Makefile.am 28 Dec 2004 05:54:24 -0000 1.1.1.1.2.1 --- Makefile.am 3 Apr 2005 20:24:00 -0000 1.1.1.1.2.2 *************** *** 1,3 **** --- 1,10 ---- + DECODER_GEN := ../decgen/decgen32 + DECODER_HDR := arm_dec.h + DECODER_DEF := arm_inst_wfpe_nonull.def + + $(DECODER_HDR): $(DECODER_DEF) + $(DECODER_GEN) -i -g 0.125 -o $@ $< + SUBDIRS = nwfpe *************** *** 34,35 **** --- 41,43 ---- INCLUDES = -I$(top_srcdir)/libosm + EXTRA_DIST = $(DECODER_DEF) arm_inst_wfpe.def Index: armemul.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/armemul.h,v retrieving revision 1.2.2.1 retrieving revision 1.2.2.2 diff -C2 -d -r1.2.2.1 -r1.2.2.2 *** armemul.h 28 Dec 2004 05:54:24 -0000 1.2.2.1 --- armemul.h 3 Apr 2005 20:24:00 -0000 1.2.2.2 *************** *** 28,31 **** --- 28,34 ---- /* run the program */ + UInt64 run(); + + /* run the program */ UInt64 run_count(UInt64 count); Index: arm_inst_wfpe_nonull.def =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/arm_inst_wfpe_nonull.def,v retrieving revision 1.1.1.1 retrieving revision 1.1.1.1.2.1 diff -C2 -d -r1.1.1.1 -r1.1.1.1.2.1 *** arm_inst_wfpe_nonull.def 24 Sep 2004 03:11:01 -0000 1.1.1.1 --- arm_inst_wfpe_nonull.def 3 Apr 2005 20:24:00 -0000 1.1.1.1.2.1 *************** *** 198,203 **** IDEF(fpe, 0x0F000000, 0x0E000000, 0.33) ! IDEF(cpld, 0x0F100E00, 0x0D100E00, 1) ! IDEF(cpst, 0x0F100E00, 0x0D000E00, 1) IDEF(sc, 0x0F000000, 0x0F000000, 1) --- 198,203 ---- IDEF(fpe, 0x0F000000, 0x0E000000, 0.33) ! /*IDEF(cpld, 0x0F100E00, 0x0D100E00, 1)*/ ! /*IDEF(cpst, 0x0F100E00, 0x0D000E00, 1)*/ IDEF(sc, 0x0F000000, 0x0F000000, 1) Index: armemul.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/emulator/armemul.cpp,v retrieving revision 1.2.2.2 retrieving revision 1.2.2.3 diff -C2 -d -r1.2.2.2 -r1.2.2.3 *** armemul.cpp 20 Feb 2005 08:14:22 -0000 1.2.2.2 --- armemul.cpp 3 Apr 2005 20:24:00 -0000 1.2.2.3 *************** *** 100,103 **** --- 100,118 ---- } + UInt64 arm_emulator::run() + { + arm_inst_t inst; + + icount = 0; + running = true; + while(running) + { + inst = fetch_inst(get_pc()); + execute(inst, get_pc()); + } + + return icount; + } + UInt64 arm_emulator::run_count(UInt64 count) { |
Update of /cvsroot/simit-arm/simit-arm/decgen In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv3564 Modified Files: Tag: sc_branch Makefile.am inst_type.h main.cpp parse_idef.y Added Files: Tag: sc_branch bin_pattern.cpp bin_pattern.hpp undef.cpp Log Message: improved decgen by allowing computing unused opcode space Index: main.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/decgen/main.cpp,v retrieving revision 1.2 retrieving revision 1.2.2.1 diff -C2 -d -r1.2 -r1.2.2.1 *** main.cpp 12 Nov 2004 06:32:59 -0000 1.2 --- main.cpp 3 Apr 2005 20:09:58 -0000 1.2.2.1 *************** *** 10,14 **** --- 10,17 ---- #include "decode_theiling.h" + using std::vector; + extern int yyparse(); + extern bool compute_undef(vector<DecodeEntry> &); using namespace std; *************** *** 29,32 **** --- 32,36 ---- << " -1bit Use only 1 bit decoding" << endl << " -theiling Use the Theiling algorithm" << endl + << " -i Compute undefined opcode space" << endl << endl; exit(1); *************** *** 51,54 **** --- 55,59 ---- char *xfname = NULL; /* output xml file */ bool theiling = false; + bool invert = false; int i; *************** *** 58,61 **** --- 63,67 ---- { if (strcmp(argv[i], "-o")==0) cfname = argv[++i]; + else if (strcmp(argv[i], "-i")==0) invert = true; else if (strcmp(argv[i], "-x")==0) xfname = argv[++i]; else if (strcmp(argv[i], "-g")==0) gamma= atof(argv[++i]); *************** *** 89,92 **** --- 95,101 ---- fclose(dec_in); + if (invert) + compute_undef(entries); + /* open output file, if any */ ofstream dec_out; Index: Makefile.am =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/decgen/Makefile.am,v retrieving revision 1.1.1.1 retrieving revision 1.1.1.1.2.1 diff -C2 -d -r1.1.1.1 -r1.1.1.1.2.1 *** Makefile.am 24 Sep 2004 03:11:00 -0000 1.1.1.1 --- Makefile.am 3 Apr 2005 20:09:58 -0000 1.1.1.1.2.1 *************** *** 28,31 **** --- 28,32 ---- decode.h decode_table.h huffman.h decode_tree.h \ decode_theiling.h \ + bin_pattern.cpp bin_pattern.hpp undef.cpp \ inst_type.h $(DECPARSE_SRC) $(DECPARSE_HDR) $(DECLEX_SRC) --- NEW FILE: undef.cpp --- /* this file is the adapter between two libraries */ #include <vector> #include <list> #include <string> #include "decode.h" #include "bin_pattern.hpp" using std::list; using std::vector; using std::string; static BinPattern entry2pattern(DecodeEntry& entry) { int ii; int nbits = INSTSIZE * 8; string spat; for (ii=nbits-1; ii>=0; ii--) { if (!entry.mask.bit_n(ii)) { spat += '-'; } else if (entry.signature.bit_n(ii)) { spat += '1'; } else { spat += '0'; } } return BinPattern(spat); } static DecodeEntry pattern2entry(BinPattern& pat) { string mask = "0x" + pat.get_hex_mask(); string sign = "0x" + pat.get_hex_signature(); return DecodeEntry(mask.c_str(), sign.c_str(), "null", 1e-10); } bool compute_undef(vector<DecodeEntry>& entries) { list<BinPattern> pats; vector<DecodeEntry>::iterator ent_it; for (ent_it = entries.begin(); ent_it!=entries.end(); ent_it++) { pats.push_back(entry2pattern(*ent_it)); } list<BinPattern> results; inverse(pats, results); // augment the original entries with null ones list<BinPattern>::iterator pat_it; for (pat_it = results.begin(); pat_it!=results.end(); pat_it++) { entries.push_back(pattern2entry(*pat_it)); } } --- NEW FILE: bin_pattern.cpp --- #include "bin_pattern.hpp" #include <cstring> using std::ostream; using std::string; using std::list; #define BITS_PER_UNSIGNED (sizeof(unsigned)*8) #define BYTES_PER_UNSIGNED (sizeof(unsigned)) static unsigned pop_count(unsigned val) { static unsigned char pop_count_table[] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8, }; unsigned count = 0; for (unsigned ii=0; ii<BYTES_PER_UNSIGNED; ii++) { count += pop_count_table[(unsigned char)val]; val >>= 8; } return count; } binary_pattern::binary_pattern(const string& str) { len = str.length(); /* allocate space for the data */ unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; data = new unsigned[wlen*2]; /* reset the data to zero */ memset(data, 0, wlen*2*BYTES_PER_UNSIGNED); const char *cstr = str.c_str(); for (unsigned ii=0; ii<len; ii++) { unsigned wpos = ii/BITS_PER_UNSIGNED; unsigned bpos = ii%BITS_PER_UNSIGNED; if (cstr[len-ii-1]=='1') { data[wpos] |= 1<<bpos; data[wlen+wpos] |= 1<<bpos; } else if (cstr[len-ii-1]=='0') { data[wpos] |= 1<<bpos; } } } binary_pattern::binary_pattern(unsigned length) : len(length) { /* allocate space for the data */ unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; data = new unsigned[wlen*2]; /* reset the data to zero */ memset(data, 0, wlen*2*BYTES_PER_UNSIGNED); } binary_pattern::binary_pattern(const binary_pattern& pat) { len = pat.len; /* allocate space for the data */ unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; data = new unsigned[wlen*2]; /* copy the data */ memcpy(data, pat.data, wlen*2*BYTES_PER_UNSIGNED); } binary_pattern::~binary_pattern() { delete [] data; } binary_pattern& binary_pattern::operator = (const binary_pattern& pat) { if (len==pat.len) { unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; memcpy(data, pat.data, wlen*2*BYTES_PER_UNSIGNED); } else { delete [] data; len = pat.len; /* allocate space for the data */ unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; data = new unsigned[wlen*2]; /* copy the data */ memcpy(data, pat.data, wlen*2*BYTES_PER_UNSIGNED); } return *this; } bool binary_pattern::overlap(const binary_pattern &pat) const { assert(len==pat.len); /* allocate space for the data */ unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; /* check all words */ for (unsigned ii=0; ii<wlen; ii++) { /* consider bits that are significant for both */ unsigned mask = data[ii] & pat.data[ii]; unsigned sig = data[wlen+ii] ^ pat.data[wlen+ii]; /* see if there is conflict */ if (mask & sig) return false; } return true; } bool binary_pattern::contain(const binary_pattern& pat) const { assert(len==pat.len); /* allocate space for the data */ unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; /* check all words */ for (unsigned ii=0; ii<wlen; ii++) { /* see if mask1 is smaller all mask2 */ if ((data[ii] & pat.data[ii]) != data[ii]) return false; /* if there is difference in value, see if significant */ unsigned sig = data[wlen+ii] ^ pat.data[wlen+ii]; if (data[ii] & sig) return false; } return true; } unsigned binary_pattern::distance(const binary_pattern& pat) const { assert(len==pat.len); /* allocate space for the data */ unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; unsigned dist = 0; /* check all words */ for (unsigned ii=0; ii<wlen; ii++) { /* consider bits that are significant for both */ unsigned mask = data[ii] & pat.data[ii]; unsigned sig = data[wlen+ii] ^ pat.data[wlen+ii]; /* see if there is conflict */ dist += pop_count(mask & sig); } return dist; } bool binary_pattern::mergeable(const binary_pattern& pat) const { assert(len==pat.len); /* allocate space for the data */ unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; unsigned dist = 0; unsigned overflow1 = 0, overflow2 = 0; /* check all words */ for (unsigned ii=0; ii<wlen; ii++) { /* consider bits that are significant for both */ unsigned mask = data[ii] & pat.data[ii]; unsigned sig = data[wlen+ii] ^ pat.data[wlen+ii]; overflow1 |= data[ii] & ~mask; overflow2 |= pat.data[ii] & ~mask; /* see if there is conflict */ dist += pop_count(mask & sig); } if (overflow1 && overflow2) return false; return dist==1; } #if 0 list<BinPattern> binary_pattern::diff(const binary_pattern& x) const { assert(this->contain(x)); list<BinPattern> ret; const char *str1 = this->data.c_str(); const char *str2 = x.data.c_str(); for (unsigned int i = 0; i<this->get_length(); i++) { if (str1[i]=='-' && str2[i]=='0') { string s(str1); s[i] = '1'; ret.push_back(s); } else if (str1[i]=='-' && str2[i]=='1') { string s(str1); s[i] = '0'; ret.push_back(s); } } return ret; } string binary_pattern::get_mask() const { string ret = data; for (unsigned int i=0; i<data.length(); i++) { if (ret[i]=='-') ret[i] = '0'; else ret[i] = '1'; } return ret; } string binary_pattern::get_signature() const { string ret = data; for (unsigned int i=0; i<data.length(); i++) { if (ret[i]=='-') ret[i] = '0'; } return ret; } #endif #define hex_char(_v) ((_v<10)?(_v+'0'):(_v+'A'-10)) string binary_pattern::get_str() const { string ret(len, '-'); unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; for (unsigned ii=0; ii<len; ii++) { unsigned wpos = ii/BITS_PER_UNSIGNED; unsigned bpos = ii%BITS_PER_UNSIGNED; if (data[wpos] & (1<<bpos)) { if (data[wpos+wlen] & (1<<bpos)) ret[len-ii-1] = '1'; else ret[len-ii-1] = '0'; } } return ret; } string binary_pattern::get_hex_mask() const { /* length of the pattern in hexidecimal */ unsigned hlen = (len+3)/4; string ret(hlen, '0'); for (unsigned ii=0; ii<len; ii+=4, hlen--) { unsigned wpos = ii/BITS_PER_UNSIGNED; unsigned bpos = ii%BITS_PER_UNSIGNED; unsigned val = (data[wpos]>>bpos) & 15; ret[hlen-1] = hex_char(val); } return ret; } string binary_pattern::get_hex_signature() const { /* length of the pattern in hexidecimal */ unsigned hlen = (len+3)/4; string ret(hlen, '0'); unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; for (unsigned ii=0; ii<len; ii+=4, hlen--) { unsigned wpos = ii/BITS_PER_UNSIGNED; unsigned bpos = ii%BITS_PER_UNSIGNED; unsigned val = (data[wpos+wlen]>>bpos) & 15; ret[hlen-1] = hex_char(val); } return ret; } ostream& binary_pattern::print(ostream& os) const { return os << this->get_str(); } const BinPattern operator + (const BinPattern& x, const BinPattern& y) { /* get the total length */ unsigned len = x.len + y.len; BinPattern result(len); /* copy the data from the low order bits*/ unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; unsigned ywlen = (y.len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; unsigned xwlen = (x.len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; /* copy over the LSBs */ memcpy(result.data, y.data, ywlen*BYTES_PER_UNSIGNED); memcpy(result.data+wlen, y.data+ywlen, ywlen*BYTES_PER_UNSIGNED); if (y.len%BITS_PER_UNSIGNED==0) { memcpy(result.data+ywlen, x.data, xwlen*BYTES_PER_UNSIGNED); memcpy(result.data+ywlen+wlen, x.data+xwlen, xwlen*BYTES_PER_UNSIGNED); } else { /* the position for the lsb from x*/ unsigned bpos = y.len%BITS_PER_UNSIGNED; for (unsigned ii=0; ii<xwlen; ii++) { result.data[ywlen-1+ii] |= x.data[ii] << bpos; result.data[wlen+ywlen-1+ii] |= x.data[ii+xwlen] << bpos; if (ywlen+ii<wlen) { result.data[ywlen+ii] |= x.data[ii] >> (BITS_PER_UNSIGNED-bpos); result.data[wlen+ywlen+ii] |= x.data[ii+xwlen] >> (BITS_PER_UNSIGNED-bpos); } } } return result; } const BinPattern operator ^ (const BinPattern& x, const BinPattern& y) { assert(x.len == y.len); BinPattern result(x.len); unsigned wlen = (x.len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; for (unsigned ii=0; ii<wlen; ii++) { /* consider bits that are significant for both */ unsigned mask = x.data[ii] & y.data[ii]; unsigned sig = x.data[wlen+ii] ^ y.data[wlen+ii]; unsigned diff = mask & sig; result.data[ii] = (x.data[ii] | y.data[ii]) & (~diff); result.data[ii+wlen] = (x.data[wlen+ii] | y.data[wlen+ii]) & (~diff); } return result; } bool operator == (const BinPattern& x, const BinPattern& y) { assert(x.len == y.len); unsigned wlen = (x.len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; for (unsigned ii=0; ii<wlen; ii++) { if (x.data[ii]!=y.data[ii]) return false; if (x.data[ii+wlen]!=y.data[ii+wlen]) return false; } return true; } bool operator != (const BinPattern& x, const BinPattern& y) { return !(x==y); } ostream& operator << (ostream& os, const BinPattern& x) { return os << x.get_str(); } static void SCC_minimal(list<binary_pattern>& pats) { list<binary_pattern>::iterator iit, jjt; for (iit=pats.begin(); iit!=pats.end();) { bool del = false; for (jjt=iit, jjt++; jjt!=pats.end();) { if ((*iit).contain(*jjt)) { jjt = pats.erase(jjt); } else if ((*jjt).contain(*iit)) { del = true; iit = pats.erase(iit); break; } else { jjt++; } } if (!del) iit++; } } static void iterated_merge(list<binary_pattern>& pats) { bool change = true; while (change) { change = false; /* remove nonessential ones first */ SCC_minimal(pats); list<binary_pattern> new_pats; list<binary_pattern>::iterator iit, jjt; for (iit=pats.begin(); iit!=pats.end();) { bool del = false; for (jjt=iit, jjt++; jjt!=pats.end();) { /* see if possible to merge */ if ((*iit).mergeable(*jjt)) { change = true; /* merge and push it to the back of the back */ new_pats.push_back((*iit)^(*jjt)); /* see if the result contains its sources */ if (new_pats.back().contain(*jjt)) { jjt = pats.erase(jjt); } else if (new_pats.back().contain(*iit)) { del = true; iit = pats.erase(iit); break; } else { assert(0); jjt++; } } else jjt++; } if (!del) iit++; } pats.insert(pats.end(), new_pats.begin(), new_pats.end()); } } void exclude_cube(list<binary_pattern>& pats, const binary_pattern& x) { assert(pats.size()>0); unsigned len = pats.front().get_length(); unsigned wlen = (len+BITS_PER_UNSIGNED-1)/BITS_PER_UNSIGNED; list<binary_pattern>::iterator iit; for (iit=pats.begin(); iit!=pats.end();) { /* the simplest case, remove iit */ if (x.contain(*iit)) { iit = pats.erase(iit); } else if ((*iit).overlap(x)) { for (unsigned ii=0; ii<wlen; ii++) { unsigned diff = ~(*iit).data[ii] & x.data[ii]; unsigned inv = ~x.data[wlen+ii]; for (unsigned jj=0; diff; jj++, diff>>=1) { if (diff&1) { BinPattern new_pat = *iit; new_pat.data[ii] |= 1<<jj; new_pat.data[ii+wlen] |= inv & (1<<jj); pats.push_back(new_pat); } } } iit = pats.erase(iit); } else iit++; } } /* get the inverse of the cubes */ void inverse(list<binary_pattern>& pats, list<binary_pattern>& result) { /* simplify the space first */ iterated_merge(pats); assert(pats.size()>0); unsigned len = pats.front().len; /* the full space */ result.push_back(binary_pattern(len)); unsigned ii=0; list<binary_pattern>::iterator iit; for (iit=pats.begin(); iit!=pats.end(); iit++, ii++) { exclude_cube(result, *iit); if (ii==5) { SCC_minimal(result); ii=0; } } /* simplify the final result */ iterated_merge(result); } Index: parse_idef.y =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/decgen/parse_idef.y,v retrieving revision 1.2 retrieving revision 1.2.2.1 diff -C2 -d -r1.2 -r1.2.2.1 *** parse_idef.y 12 Nov 2004 06:32:59 -0000 1.2 --- parse_idef.y 3 Apr 2005 20:09:58 -0000 1.2.2.1 *************** *** 49,53 **** void yyerror (char *s) { ! std::cerr << s << "near line " << mylineno+1 << std::endl; } --- 49,53 ---- void yyerror (char *s) { ! std::cerr << s << " near line " << mylineno+1 << std::endl; } Index: inst_type.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/decgen/inst_type.h,v retrieving revision 1.2 retrieving revision 1.2.2.1 diff -C2 -d -r1.2 -r1.2.2.1 *** inst_type.h 12 Nov 2004 06:32:59 -0000 1.2 --- inst_type.h 3 Apr 2005 20:09:58 -0000 1.2.2.1 *************** *** 55,58 **** --- 55,60 ---- unsigned int ucast() const {return (unsigned int)val;} + bool bit_n(unsigned n) {return (val>>n)&1;} + private: *************** *** 133,136 **** --- 135,140 ---- unsigned int ucast() const {return (unsigned int)val;} + bool bit_n(unsigned n) {return (val>>n)&1;} + private: --- NEW FILE: bin_pattern.hpp --- #ifndef __MAD_BIN_PATTERN_HPP__ #define __MAD_BIN_PATTERN_HPP__ #include <iostream> #include <string> #include <cassert> #include <list> #include "config.h" /** binary pattern class. */ typedef class binary_pattern { public: /** Constructor. */ binary_pattern(const std::string& d); /** Constructor. */ binary_pattern(unsigned len); /** Copy constructor. */ binary_pattern(const binary_pattern& pat); /** Destructor. */ ~binary_pattern(); /** Assignment operator */ binary_pattern& operator = (const binary_pattern& pat); /** Get the length of the pattern. */ unsigned get_length() const {return len;} /** Distance between patterns (number of conflicting bits) */ unsigned distance(const binary_pattern& pat) const; bool mergeable(const binary_pattern& pat) const; /** Check if this pattern contains the other. */ bool contain(const binary_pattern& pat) const; /** Overlap is weaker than contains. */ bool overlap(const binary_pattern& pat) const; #if 0 /** return a difference vector A-B. */ std::vector<binary_pattern> diff(const binary_pattern& pat) const; /** Get the mask of the pattern, in binary format. */ std::string get_mask() const; /** Get the signature of the pattern, in binary format. */ std::string get_signature() const; #endif /** Get the string representing the pattern, in '0', '1', '-' */ std::string get_str() const; /** Get the mask of the pattern, in hexadecimal w/o 0x. */ std::string get_hex_mask() const; /** Get the signature of the pattern, in hexadecimal w/o 0x. */ std::string get_hex_signature() const; /** Output the pattern. */ std::ostream& print(std::ostream& os) const; private: /* pointer to array of masks and signatures (mask first) * data[0]'s LSB is the lowest bit */ unsigned *data; /* length of the pattern */ unsigned len; friend const binary_pattern operator + (const binary_pattern& x, const binary_pattern& y); friend const binary_pattern operator ^ (const binary_pattern& x, const binary_pattern& y); friend bool operator == (const binary_pattern& x, const binary_pattern& y); friend bool operator != (const binary_pattern& x, const binary_pattern& y); friend void inverse(std::list<binary_pattern>& pats, std::list<binary_pattern>& result); friend void exclude_cube(std::list<binary_pattern>& pats, const binary_pattern& cube); } BinPattern; /** Concatenate two patterns. * @param x The high order bits. * @param y The low order bits. */ const binary_pattern operator + (const binary_pattern& x, const binary_pattern& y); /** Consensus of two patterns. */ const binary_pattern operator ^ (const binary_pattern& x, const binary_pattern& y); /** The equality operator */ bool operator == (const BinPattern& x, const BinPattern& y); /** The inequality operator */ bool operator != (const BinPattern& x, const BinPattern& y); /** Inverion of the boolean space. * @param pats The original space. * @param result The inverted space. */ void inverse(std::list<binary_pattern>& pats, std::list<binary_pattern>& result); /** Exclude a cube from a list of cubes. * @param pats The cubes to work on. * @param cube The cube to exclude. */ void exclude_cube(std::list<binary_pattern>& pats, const binary_pattern& cube); /** Output the pattern. */ std::ostream& operator << (std::ostream& os, const BinPattern& x); #endif |
