[Simit-arm-cvs] simit-arm/simulator/src arm.mad,1.3,1.4 ldst.mad,1.4,1.5

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Update of /cvsroot/simit-arm/simit-arm/simulator/src
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv1880/src

Modified Files:
	arm.mad ldst.mad 
Log Message:
added support for smp simulation, implemented swp swpb instructions

Index: ldst.mad
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/src/ldst.mad,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** ldst.mad	2 Feb 2005 17:53:35 -0000	1.4
--- ldst.mad	23 Aug 2005 19:47:52 -0000	1.5
***************
*** 35,39 ****
  		off_str = imm.dec;
  		+opcd;
! 		mode = mem_size << 1;
  
  	TRANS
--- 35,39 ----
  		off_str = imm.dec;
  		+opcd;
! 		mode = (mem_size << 2) | 2;
  
  	TRANS
***************
*** 76,80 ****
  		off_str = shift.syn;
  		+opcd;
! 		mode = mem_size << 1;
  
  	TRANS
--- 76,80 ----
  		off_str = shift.syn;
  		+opcd;
! 		mode = (mem_size << 2) | 2;
  
  	TRANS
***************
*** 124,128 ****
  		+opcd;
  		m_size = h_uint?2:1;
! 		mode = h_uint?4:2;
  
  	TRANS
--- 124,128 ----
  		+opcd;
  		m_size = h_uint?2:1;
! 		mode = h_uint?10:6;
  
  	TRANS
***************
*** 176,180 ****
  		+opcd;
  		m_size = h_uint?2:1;
! 		mode = h_uint?4:2;
  
  	TRANS
--- 176,180 ----
  		+opcd;
  		m_size = h_uint?2:1;
! 		mode = h_uint?10:6;
  
  	TRANS
***************
*** 227,231 ****
  		off_str = imm.dec;
  		+opcd;
! 		mode = (mem_size << 1) | 1;
  
  	TRANS
--- 227,231 ----
  		off_str = imm.dec;
  		+opcd;
! 		mode = (mem_size << 2) | 1;
  
  	TRANS
***************
*** 268,272 ****
  		off_str = shift.syn;
  		+opcd;
! 		mode = (mem_size << 1) | 1;
  
  	TRANS
--- 268,272 ----
  		off_str = shift.syn;
  		+opcd;
! 		mode = (mem_size << 2) | 1;
  
  	TRANS
***************
*** 315,319 ****
  		+opcd;
  		m_size = h_uint?2:1;
! 		mode = h_uint?5:3;
  
  	TRANS
--- 315,319 ----
  		+opcd;
  		m_size = h_uint?2:1;
! 		mode = h_uint?9:5;
  
  	TRANS
***************
*** 361,365 ****
  		+opcd;
  		m_size = h_uint?2:1;
! 		mode = h_uint?5:3;
  
  	TRANS
--- 361,365 ----
  		+opcd;
  		m_size = h_uint?2:1;
! 		mode = h_uint?9:5;
  
  	TRANS
***************
*** 562,572 ****
  	e_ex_bf:	{pred>0,
  				 bf_buffer = mBF[], !ex_buffer,
! 				 *mMemAddr[] = v_rn, *mMemCtrl[] = 8};
  
! 	e_bf_bf_post:   {*mMemCtrl[], v_rd = *mMemRead[],
! 					 *mMemWrite[] = v_rm, *mMemCtrl[] = 9};
  
! 	e_bf_post_wb:  	{*mMemCtrl[], wb_buffer = mWB[], !bf_buffer,
! 					 *dst_buffer = v_rd, !dst_buffer, *mReset[]=(rd,1)};
  
  	e_wb_in:		{!wb_buffer};
--- 562,598 ----
  	e_ex_bf:	{pred>0,
  				 bf_buffer = mBF[], !ex_buffer,
! 				 *mMemAddr[] = v_rn, *mMemWrite[] = v_rm, *mMemCtrl[] = 19};
  
! 	e_bf_wb:	{wb_buffer = mWB[], !bf_buffer, *mMemCtrl[],
! 				 *dst_buffer = *mMemRead[], !dst_buffer, *mReset[]=(rd,1)};
  
! 	e_wb_in:		{!wb_buffer};
! 
! 	e_ex_bf_null:   {pred==0, bf_buffer = mBF[], !!ex_buffer, !!dst_buffer};
! 	e_bf_wb_null:   {wb_buffer = mWB[], !!bf_buffer};
! 	e_wb_in_null:   {!!wb_buffer};
! 
! 	e_ex_in:        {*mReset[], !!ex_buffer, !!dst_buffer};
! 
! 
! OPERATION swapb
! 
! 	SYNTAX "swp" ^ cond_names[cond] ^ "b" reg_names[rd]^"," reg_names[rn]^", ["
! 			reg_names[rn]^"]";
! 	CODING cond 000101 00 rn rd 0000 1001 rm ;
! 
! 	TRANS
! 	e_id_ex:   {ex_buffer = mEX[], !id_buffer,
! 				v_rm = *mRF[rm], v_rn = *mRF[rn], dst_buffer = mRF[rd],
! 				v_iflag = *mCPSR[]}
! 
! 				eval_pred(pred, cond, v_iflag);
! 
! 	e_ex_bf:	{pred>0,
! 				 bf_buffer = mBF[], !ex_buffer,
! 				 *mMemAddr[] = v_rn, *mMemWrite[] = v_rm, *mMemCtrl[] = 7};
! 
! 	e_bf_wb:	{wb_buffer = mWB[], !bf_buffer, *mMemCtrl[],
! 				 *dst_buffer = *mMemRead[], !dst_buffer, *mReset[]=(rd,1)};
  
  	e_wb_in:		{!wb_buffer};
***************
*** 647,651 ****
  		rmb(i0, rinds, 0);
  		popcount16(bcount, rinds);
! 		mode = (bcount << 4) | 8;
  		+wbit;
  
--- 673,677 ----
  		rmb(i0, rinds, 0);
  		popcount16(bcount, rinds);
! 		mode = (bcount << 5) | 18;
  		+wbit;
  
***************
*** 815,819 ****
  		rmb(i14, rinds, i0+1);
  		popcount16(bcount, rinds);
! 		mode = (bcount << 4) | 9;
  		+wbit;
  
--- 841,845 ----
  		rmb(i14, rinds, i0+1);
  		popcount16(bcount, rinds);
! 		mode = (bcount << 5) | 17;
  		+wbit;
  
***************
*** 947,949 ****
  	e_wb_in:   {!wb_buffer};
  
- 
--- 973,974 ----

Index: arm.mad
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/src/arm.mad,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** arm.mad	19 Aug 2005 03:15:07 -0000	1.3
--- arm.mad	23 Aug 2005 19:47:52 -0000	1.4
***************
*** 77,81 ****
  		mem_read_port  : void -> uint<32>;
  		mem_write_port : void -> uint<32>;
! 		mem_ctrl_port  : void -> uint<32>; # count :: size(3bit) :: r/w (1bit)
  
  		# new pc, written by branch operation
--- 77,81 ----
  		mem_read_port  : void -> uint<32>;
  		mem_write_port : void -> uint<32>;
! 		mem_ctrl_port  : void -> uint<32>; # count :: size(3bit) :: r :: w 
  
  		# new pc, written by branch operation
***************
*** 263,267 ****
  			  load_imm, load_reg, load_ext_imm, load_ext_reg,
  			  store_imm, store_reg, store_ext_imm, store_ext_reg,
! 			  swap, ldm, stm,
  			  mult, mult_long, syscall, 
  			  coproc_inst}(unknown); # unknown as the default
--- 263,267 ----
  			  load_imm, load_reg, load_ext_imm, load_ext_reg,
  			  store_imm, store_reg, store_ext_imm, store_ext_reg,
! 			  swap, swapb, ldm, stm,
  			  mult, mult_long, syscall, 
  			  coproc_inst}(unknown); # unknown as the default