[Simit-arm-cvs] simit-arm/simulator biu.h,NONE,1.1 Makefile.am,1.5,1.6 armsim.cpp,1.7,1.8 armsim.hpp,1.5,1.6 biu.cpp,1.1,1.2 cache.h,1.6,1.7 fetch_oper_pat.hpp,1.5,1.6 fetch_oper_tab.hpp,1.3,1.4 machines.cpp,1.6,1.7 machines.hpp,1.3,1.4 main.cpp,1.6,1.7 mcu.hpp,1.1,1.2 more_managers.cpp,1.3,1.4 more_managers.hpp,1.4,1.5

[Wei Q. <wei...@us...>]

Update of /cvsroot/simit-arm/simit-arm/simulator
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv1880

Modified Files:
	Makefile.am armsim.cpp armsim.hpp biu.cpp cache.h 
	fetch_oper_pat.hpp fetch_oper_tab.hpp machines.cpp 
	machines.hpp main.cpp mcu.hpp more_managers.cpp 
	more_managers.hpp 
Added Files:
	biu.h 
Log Message:
added support for smp simulation, implemented swp swpb instructions

Index: machines.hpp
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/machines.hpp,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** machines.hpp	19 Aug 2005 03:15:05 -0000	1.3
--- machines.hpp	23 Aug 2005 19:47:52 -0000	1.4
***************
*** 1135,1254 ****
        L_$S_EX$36821,	/*1121*/
        L_$S_BF$36823,	/*1122*/
!       L_$S_BF_POST$36841,	/*1123*/
!       L_$S_ID$36890,	/*1124*/
!       L_$S_EX$36891,	/*1125*/
!       L_$S_B0$36895,	/*1126*/
!       L_$S_B2$36896,	/*1127*/
!       L_$S_B3$36897,	/*1128*/
!       L_$S_B4$36898,	/*1129*/
!       L_$S_B5$36899,	/*1130*/
!       L_$S_B6$36900,	/*1131*/
!       L_$S_B7$36901,	/*1132*/
!       L_$S_B8$36902,	/*1133*/
!       L_$S_B9$36903,	/*1134*/
!       L_$S_B10$36904,	/*1135*/
!       L_$S_B11$36905,	/*1136*/
!       L_$S_B12$36906,	/*1137*/
!       L_$S_B13$36907,	/*1138*/
!       L_$S_B14$36908,	/*1139*/
!       L_$S_B15$36909,	/*1140*/
!       L_$S_B1$36913,	/*1141*/
!       L_$S_ID$36960,	/*1142*/
!       L_$S_EX$36961,	/*1143*/
!       L_$S_B0$36965,	/*1144*/
!       L_$S_B2$36966,	/*1145*/
!       L_$S_B3$36967,	/*1146*/
!       L_$S_B4$36968,	/*1147*/
!       L_$S_B5$36969,	/*1148*/
!       L_$S_B6$36970,	/*1149*/
!       L_$S_B7$36971,	/*1150*/
!       L_$S_B8$36972,	/*1151*/
!       L_$S_B9$36973,	/*1152*/
!       L_$S_B10$36974,	/*1153*/
!       L_$S_B11$36975,	/*1154*/
!       L_$S_B12$36976,	/*1155*/
!       L_$S_B13$36977,	/*1156*/
!       L_$S_B14$36978,	/*1157*/
!       L_$S_B15$36979,	/*1158*/
!       L_$S_ID$37030,	/*1159*/
!       L_$S_EX$37031,	/*1160*/
!       L_$S_B0$37035,	/*1161*/
!       L_$S_B2$37036,	/*1162*/
!       L_$S_B3$37037,	/*1163*/
!       L_$S_B4$37038,	/*1164*/
!       L_$S_B5$37039,	/*1165*/
!       L_$S_B6$37040,	/*1166*/
!       L_$S_B7$37041,	/*1167*/
!       L_$S_B8$37042,	/*1168*/
!       L_$S_B9$37043,	/*1169*/
!       L_$S_B10$37044,	/*1170*/
!       L_$S_B11$37045,	/*1171*/
!       L_$S_B12$37046,	/*1172*/
!       L_$S_B13$37047,	/*1173*/
!       L_$S_B14$37048,	/*1174*/
!       L_$S_B15$37049,	/*1175*/
!       L_$S_B1$37053,	/*1176*/
!       L_$S_ID$37100,	/*1177*/
!       L_$S_EX$37101,	/*1178*/
!       L_$S_B0$37105,	/*1179*/
!       L_$S_B2$37106,	/*1180*/
!       L_$S_B3$37107,	/*1181*/
!       L_$S_B4$37108,	/*1182*/
!       L_$S_B5$37109,	/*1183*/
!       L_$S_B6$37110,	/*1184*/
!       L_$S_B7$37111,	/*1185*/
!       L_$S_B8$37112,	/*1186*/
!       L_$S_B9$37113,	/*1187*/
!       L_$S_B10$37114,	/*1188*/
!       L_$S_B11$37115,	/*1189*/
!       L_$S_B12$37116,	/*1190*/
!       L_$S_B13$37117,	/*1191*/
!       L_$S_B14$37118,	/*1192*/
!       L_$S_B15$37119,	/*1193*/
!       L_$S_ID$37170,	/*1194*/
!       L_$S_EX$37171,	/*1195*/
!       L_$S_BF$37173,	/*1196*/
!       L_$S_BF_NULL$37174,	/*1197*/
!       L_$S_WB_NULL$37192,	/*1198*/
!       L_$S_ID$37240,	/*1199*/
!       L_$S_EX$37241,	/*1200*/
!       L_$S_ID$37310,	/*1201*/
!       L_$S_EX$37311,	/*1202*/
!       L_$S_ID$37380,	/*1203*/
!       L_$S_EX$37381,	/*1204*/
!       L_$S_ID$37450,	/*1205*/
!       L_$S_EX$37451,	/*1206*/
!       L_$S_BF$37453,	/*1207*/
!       L_$S_BF_POST$37471,	/*1208*/
!       L_$S_ID$37520,	/*1209*/
!       L_$S_EX$37521,	/*1210*/
!       L_$S_BF$37523,	/*1211*/
!       L_$S_ID$37590,	/*1212*/
!       L_$S_EX$37591,	/*1213*/
!       L_$S_ID$37660,	/*1214*/
!       L_$S_EX$37661,	/*1215*/
!       L_$S_ID$37730,	/*1216*/
!       L_$S_EX$37731,	/*1217*/
!       L_$S_ID$37800,	/*1218*/
!       L_$S_EX$37801,	/*1219*/
!       L_$S_ID$37870,	/*1220*/
!       L_$S_EX$37871,	/*1221*/
!       L_$S_ID$37940,	/*1222*/
!       L_$S_EX$37941,	/*1223*/
!       L_$S_ID$38010,	/*1224*/
!       L_$S_EX$38011,	/*1225*/
!       L_$S_BF$38013,	/*1226*/
!       L_$S_WB$38030,	/*1227*/
!       L_$S_ID$38080,	/*1228*/
!       L_$S_EX$38081,	/*1229*/
!       L_$S_BF$38083,	/*1230*/
!       L_$S_WB$38100,	/*1231*/
!       L_$S_ID$38150,	/*1232*/
        L_$S_ID$38220,	/*1233*/
        L_$S_ID$38290,	/*1234*/
        L_$S_ID$38360,	/*1235*/
        L_$S_ID$38430,	/*1236*/
!       L_$S_EX$38431,	/*1237*/
!       L_$S_BF$38433,	/*1238*/
      };
  
--- 1135,1255 ----
        L_$S_EX$36821,	/*1121*/
        L_$S_BF$36823,	/*1122*/
!       L_$S_ID$36890,	/*1123*/
!       L_$S_EX$36891,	/*1124*/
!       L_$S_ID$36960,	/*1125*/
!       L_$S_EX$36961,	/*1126*/
!       L_$S_B0$36965,	/*1127*/
!       L_$S_B2$36966,	/*1128*/
!       L_$S_B3$36967,	/*1129*/
!       L_$S_B4$36968,	/*1130*/
!       L_$S_B5$36969,	/*1131*/
!       L_$S_B6$36970,	/*1132*/
!       L_$S_B7$36971,	/*1133*/
!       L_$S_B8$36972,	/*1134*/
!       L_$S_B9$36973,	/*1135*/
!       L_$S_B10$36974,	/*1136*/
!       L_$S_B11$36975,	/*1137*/
!       L_$S_B12$36976,	/*1138*/
!       L_$S_B13$36977,	/*1139*/
!       L_$S_B14$36978,	/*1140*/
!       L_$S_B15$36979,	/*1141*/
!       L_$S_B1$36983,	/*1142*/
!       L_$S_ID$37030,	/*1143*/
!       L_$S_EX$37031,	/*1144*/
!       L_$S_B0$37035,	/*1145*/
!       L_$S_B2$37036,	/*1146*/
!       L_$S_B3$37037,	/*1147*/
!       L_$S_B4$37038,	/*1148*/
!       L_$S_B5$37039,	/*1149*/
!       L_$S_B6$37040,	/*1150*/
!       L_$S_B7$37041,	/*1151*/
!       L_$S_B8$37042,	/*1152*/
!       L_$S_B9$37043,	/*1153*/
!       L_$S_B10$37044,	/*1154*/
!       L_$S_B11$37045,	/*1155*/
!       L_$S_B12$37046,	/*1156*/
!       L_$S_B13$37047,	/*1157*/
!       L_$S_B14$37048,	/*1158*/
!       L_$S_B15$37049,	/*1159*/
!       L_$S_ID$37100,	/*1160*/
!       L_$S_EX$37101,	/*1161*/
!       L_$S_B0$37105,	/*1162*/
!       L_$S_B2$37106,	/*1163*/
!       L_$S_B3$37107,	/*1164*/
!       L_$S_B4$37108,	/*1165*/
!       L_$S_B5$37109,	/*1166*/
!       L_$S_B6$37110,	/*1167*/
!       L_$S_B7$37111,	/*1168*/
!       L_$S_B8$37112,	/*1169*/
!       L_$S_B9$37113,	/*1170*/
!       L_$S_B10$37114,	/*1171*/
!       L_$S_B11$37115,	/*1172*/
!       L_$S_B12$37116,	/*1173*/
!       L_$S_B13$37117,	/*1174*/
!       L_$S_B14$37118,	/*1175*/
!       L_$S_B15$37119,	/*1176*/
!       L_$S_B1$37123,	/*1177*/
!       L_$S_ID$37170,	/*1178*/
!       L_$S_EX$37171,	/*1179*/
!       L_$S_B0$37175,	/*1180*/
!       L_$S_B2$37176,	/*1181*/
!       L_$S_B3$37177,	/*1182*/
!       L_$S_B4$37178,	/*1183*/
!       L_$S_B5$37179,	/*1184*/
!       L_$S_B6$37180,	/*1185*/
!       L_$S_B7$37181,	/*1186*/
!       L_$S_B8$37182,	/*1187*/
!       L_$S_B9$37183,	/*1188*/
!       L_$S_B10$37184,	/*1189*/
!       L_$S_B11$37185,	/*1190*/
!       L_$S_B12$37186,	/*1191*/
!       L_$S_B13$37187,	/*1192*/
!       L_$S_B14$37188,	/*1193*/
!       L_$S_B15$37189,	/*1194*/
!       L_$S_ID$37240,	/*1195*/
!       L_$S_EX$37241,	/*1196*/
!       L_$S_BF$37243,	/*1197*/
!       L_$S_BF_NULL$37244,	/*1198*/
!       L_$S_WB_NULL$37262,	/*1199*/
!       L_$S_ID$37310,	/*1200*/
!       L_$S_EX$37311,	/*1201*/
!       L_$S_ID$37380,	/*1202*/
!       L_$S_EX$37381,	/*1203*/
!       L_$S_ID$37450,	/*1204*/
!       L_$S_EX$37451,	/*1205*/
!       L_$S_ID$37520,	/*1206*/
!       L_$S_EX$37521,	/*1207*/
!       L_$S_BF$37523,	/*1208*/
!       L_$S_BF_POST$37541,	/*1209*/
!       L_$S_ID$37590,	/*1210*/
!       L_$S_EX$37591,	/*1211*/
!       L_$S_BF$37593,	/*1212*/
!       L_$S_ID$37660,	/*1213*/
!       L_$S_EX$37661,	/*1214*/
!       L_$S_ID$37730,	/*1215*/
!       L_$S_EX$37731,	/*1216*/
!       L_$S_ID$37800,	/*1217*/
!       L_$S_EX$37801,	/*1218*/
!       L_$S_ID$37870,	/*1219*/
!       L_$S_EX$37871,	/*1220*/
!       L_$S_ID$37940,	/*1221*/
!       L_$S_EX$37941,	/*1222*/
!       L_$S_ID$38010,	/*1223*/
!       L_$S_EX$38011,	/*1224*/
!       L_$S_ID$38080,	/*1225*/
!       L_$S_EX$38081,	/*1226*/
!       L_$S_BF$38083,	/*1227*/
!       L_$S_WB$38100,	/*1228*/
!       L_$S_ID$38150,	/*1229*/
!       L_$S_EX$38151,	/*1230*/
!       L_$S_BF$38153,	/*1231*/
!       L_$S_WB$38170,	/*1232*/
        L_$S_ID$38220,	/*1233*/
        L_$S_ID$38290,	/*1234*/
        L_$S_ID$38360,	/*1235*/
        L_$S_ID$38430,	/*1236*/
!       L_$S_ID$38500,	/*1237*/
!       L_$S_EX$38501,	/*1238*/
!       L_$S_BF$38503,	/*1239*/
      };
  
***************
*** 1779,1882 ****
      bool L_$e_id_ex$36845();
      bool L_$e_ex_bf$36849();
!     bool L_$e_bf_bf_post$36869();
!     bool L_$e_bf_post_wb$36887();
      bool L_$e_id_ex$36915();
-     bool L_$e_ex_in$36918();
      bool L_$e_ex_bf$36919();
-     bool L_$e_ex_bf_null$36920();
-     bool L_$e_ex_b0$36921();
-     bool L_$e_ex_b2$36922();
-     bool L_$e_ex_b3$36923();
-     bool L_$e_ex_b4$36924();
-     bool L_$e_ex_b5$36925();
-     bool L_$e_ex_b6$36926();
-     bool L_$e_ex_b7$36927();
-     bool L_$e_ex_b8$36928();
-     bool L_$e_ex_b9$36929();
-     bool L_$e_ex_b10$36930();
-     bool L_$e_ex_b11$36931();
-     bool L_$e_ex_b12$36932();
-     bool L_$e_ex_b13$36933();
-     bool L_$e_ex_b14$36934();
-     bool L_$e_ex_b15$36935();
-     bool L_$e_b0_bf$36941();
-     bool L_$e_b2_b1$36942();
-     bool L_$e_b3_b2$36943();
-     bool L_$e_b4_b3$36944();
-     bool L_$e_b5_b4$36945();
-     bool L_$e_b6_b5$36946();
-     bool L_$e_b7_b6$36947();
-     bool L_$e_b8_b7$36948();
-     bool L_$e_b9_b8$36949();
-     bool L_$e_b10_b9$36950();
-     bool L_$e_b11_b10$36951();
-     bool L_$e_b12_b11$36952();
-     bool L_$e_b13_b12$36953();
-     bool L_$e_b14_b13$36954();
-     bool L_$e_b15_b14$36955();
-     bool L_$e_b1_wb$36959();
      bool L_$e_id_ex$36985();
      bool L_$e_ex_in$36988();
      bool L_$e_ex_bf$36989();
      bool L_$e_ex_bf_null$36990();
      bool L_$e_b0_bf$37011();
      bool L_$e_b2_b1$37012();
      bool L_$e_id_ex$37055();
      bool L_$e_ex_bf$37059();
!     bool L_$e_ex_b0$37061();
!     bool L_$e_ex_b2$37062();
!     bool L_$e_ex_b3$37063();
!     bool L_$e_ex_b4$37064();
!     bool L_$e_ex_b5$37065();
!     bool L_$e_ex_b6$37066();
!     bool L_$e_ex_b7$37067();
!     bool L_$e_ex_b8$37068();
!     bool L_$e_ex_b9$37069();
!     bool L_$e_ex_b10$37070();
!     bool L_$e_ex_b11$37071();
!     bool L_$e_ex_b12$37072();
!     bool L_$e_ex_b13$37073();
!     bool L_$e_ex_b14$37074();
!     bool L_$e_ex_b15$37075();
      bool L_$e_b0_bf$37081();
      bool L_$e_b2_b1$37082();
-     bool L_$e_b3_b2$37083();
-     bool L_$e_b4_b3$37084();
-     bool L_$e_b5_b4$37085();
-     bool L_$e_b6_b5$37086();
-     bool L_$e_b7_b6$37087();
-     bool L_$e_b8_b7$37088();
-     bool L_$e_b9_b8$37089();
-     bool L_$e_b10_b9$37090();
-     bool L_$e_b11_b10$37091();
-     bool L_$e_b12_b11$37092();
-     bool L_$e_b13_b12$37093();
-     bool L_$e_b14_b13$37094();
-     bool L_$e_b15_b14$37095();
-     bool L_$e_b1_wb$37099();
      bool L_$e_id_ex$37125();
      bool L_$e_ex_bf$37129();
      bool L_$e_b0_bf$37151();
      bool L_$e_b2_b1$37152();
      bool L_$e_id_ex$37195();
-     bool L_$e_ex_in$37198();
      bool L_$e_ex_bf$37199();
!     bool L_$e_bf_wb$37218();
!     bool L_$e_bf_wb_null$37220();
!     bool L_$e_wb_in_null$37238();
      bool L_$e_ex_bf$37269();
!     bool L_$e_id_ex$37335();
      bool L_$e_ex_bf$37339();
      bool L_$e_ex_bf$37409();
-     bool L_$e_id_ex$37475();
-     bool L_$e_ex_in$37478();
      bool L_$e_ex_bf$37479();
!     bool L_$e_ex_bf_null$37480();
!     bool L_$e_bf_bf_post$37499();
!     bool L_$e_bf_post_wb$37517();
      bool L_$e_ex_bf$37549();
      bool L_$e_bf_bf_post$37569();
!     bool L_$e_id_ex$37615();
      bool L_$e_ex_bf$37619();
      bool L_$e_ex_bf$37689();
      bool L_$e_ex_bf$37759();
--- 1780,1883 ----
      bool L_$e_id_ex$36845();
      bool L_$e_ex_bf$36849();
!     bool L_$e_bf_wb$36868();
      bool L_$e_id_ex$36915();
      bool L_$e_ex_bf$36919();
      bool L_$e_id_ex$36985();
      bool L_$e_ex_in$36988();
      bool L_$e_ex_bf$36989();
      bool L_$e_ex_bf_null$36990();
+     bool L_$e_ex_b0$36991();
+     bool L_$e_ex_b2$36992();
+     bool L_$e_ex_b3$36993();
+     bool L_$e_ex_b4$36994();
+     bool L_$e_ex_b5$36995();
+     bool L_$e_ex_b6$36996();
+     bool L_$e_ex_b7$36997();
+     bool L_$e_ex_b8$36998();
+     bool L_$e_ex_b9$36999();
+     bool L_$e_ex_b10$37000();
+     bool L_$e_ex_b11$37001();
+     bool L_$e_ex_b12$37002();
+     bool L_$e_ex_b13$37003();
+     bool L_$e_ex_b14$37004();
+     bool L_$e_ex_b15$37005();
      bool L_$e_b0_bf$37011();
      bool L_$e_b2_b1$37012();
+     bool L_$e_b3_b2$37013();
+     bool L_$e_b4_b3$37014();
+     bool L_$e_b5_b4$37015();
+     bool L_$e_b6_b5$37016();
+     bool L_$e_b7_b6$37017();
+     bool L_$e_b8_b7$37018();
+     bool L_$e_b9_b8$37019();
+     bool L_$e_b10_b9$37020();
+     bool L_$e_b11_b10$37021();
+     bool L_$e_b12_b11$37022();
+     bool L_$e_b13_b12$37023();
+     bool L_$e_b14_b13$37024();
+     bool L_$e_b15_b14$37025();
+     bool L_$e_b1_wb$37029();
      bool L_$e_id_ex$37055();
+     bool L_$e_ex_in$37058();
      bool L_$e_ex_bf$37059();
!     bool L_$e_ex_bf_null$37060();
      bool L_$e_b0_bf$37081();
      bool L_$e_b2_b1$37082();
      bool L_$e_id_ex$37125();
      bool L_$e_ex_bf$37129();
+     bool L_$e_ex_b0$37131();
+     bool L_$e_ex_b2$37132();
+     bool L_$e_ex_b3$37133();
+     bool L_$e_ex_b4$37134();
+     bool L_$e_ex_b5$37135();
+     bool L_$e_ex_b6$37136();
+     bool L_$e_ex_b7$37137();
+     bool L_$e_ex_b8$37138();
+     bool L_$e_ex_b9$37139();
+     bool L_$e_ex_b10$37140();
+     bool L_$e_ex_b11$37141();
+     bool L_$e_ex_b12$37142();
+     bool L_$e_ex_b13$37143();
+     bool L_$e_ex_b14$37144();
+     bool L_$e_ex_b15$37145();
      bool L_$e_b0_bf$37151();
      bool L_$e_b2_b1$37152();
+     bool L_$e_b3_b2$37153();
+     bool L_$e_b4_b3$37154();
+     bool L_$e_b5_b4$37155();
+     bool L_$e_b6_b5$37156();
+     bool L_$e_b7_b6$37157();
+     bool L_$e_b8_b7$37158();
+     bool L_$e_b9_b8$37159();
+     bool L_$e_b10_b9$37160();
+     bool L_$e_b11_b10$37161();
+     bool L_$e_b12_b11$37162();
+     bool L_$e_b13_b12$37163();
+     bool L_$e_b14_b13$37164();
+     bool L_$e_b15_b14$37165();
+     bool L_$e_b1_wb$37169();
      bool L_$e_id_ex$37195();
      bool L_$e_ex_bf$37199();
!     bool L_$e_b0_bf$37221();
!     bool L_$e_b2_b1$37222();
!     bool L_$e_id_ex$37265();
!     bool L_$e_ex_in$37268();
      bool L_$e_ex_bf$37269();
!     bool L_$e_bf_wb$37288();
!     bool L_$e_bf_wb_null$37290();
!     bool L_$e_wb_in_null$37308();
      bool L_$e_ex_bf$37339();
+     bool L_$e_id_ex$37405();
      bool L_$e_ex_bf$37409();
      bool L_$e_ex_bf$37479();
!     bool L_$e_id_ex$37545();
!     bool L_$e_ex_in$37548();
      bool L_$e_ex_bf$37549();
+     bool L_$e_ex_bf_null$37550();
      bool L_$e_bf_bf_post$37569();
!     bool L_$e_bf_post_wb$37587();
      bool L_$e_ex_bf$37619();
+     bool L_$e_bf_bf_post$37639();
+     bool L_$e_id_ex$37685();
      bool L_$e_ex_bf$37689();
      bool L_$e_ex_bf$37759();
***************
*** 1884,1897 ****
      bool L_$e_ex_bf$37899();
      bool L_$e_ex_bf$37969();
-     bool L_$e_id_ex$38035();
      bool L_$e_ex_bf$38039();
-     bool L_$e_bf_wb$38058();
-     bool L_$e_wb_in$38076();
      bool L_$e_id_ex$38105();
      bool L_$e_bf_wb$38128();
      bool L_$e_wb_in$38146();
!     bool L_$e_id_ex$38455();
!     bool L_$e_ex_bf$38459();
!     bool L_$e_bf_wb$38478();
  
  
--- 1885,1899 ----
      bool L_$e_ex_bf$37899();
      bool L_$e_ex_bf$37969();
      bool L_$e_ex_bf$38039();
      bool L_$e_id_ex$38105();
+     bool L_$e_ex_bf$38109();
      bool L_$e_bf_wb$38128();
      bool L_$e_wb_in$38146();
!     bool L_$e_id_ex$38175();
!     bool L_$e_bf_wb$38198();
!     bool L_$e_wb_in$38216();
!     bool L_$e_id_ex$38525();
!     bool L_$e_ex_bf$38529();
!     bool L_$e_bf_wb$38548();
  
  
***************
*** 2545,2548 ****
--- 2547,2551 ----
      void __dec_548();
      void __dec_549();
+     void __dec_550();
  };
  

Index: more_managers.hpp
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/more_managers.hpp,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** more_managers.hpp	19 Aug 2005 03:15:05 -0000	1.4
--- more_managers.hpp	23 Aug 2005 19:47:52 -0000	1.5
***************
*** 394,397 ****
--- 394,401 ----
  		unsigned get_current_pc();
  
+ 		void set_armsim(arm_simulator *armsim) {
+ 			_armsim = armsim;
+ 		}
+ 
  	private:
  
***************
*** 411,414 ****
--- 415,419 ----
  		// two flags for debugging
  		int branch_taken, first_inst;
+ 		arm_simulator *_armsim;
  
  };
***************
*** 460,466 ****
  		 */
  		void write_token(const _UINT_T(32)& val, _BASE_MACHINE *obj) {
! 			isRead = 1 - (val.val() & 1);
! 			size = (val.val()>>1)&7;
! 			count = val.val()>>4;
  			trigger = true;
  		}
--- 465,472 ----
  		 */
  		void write_token(const _UINT_T(32)& val, _BASE_MACHINE *obj) {
! 			isRead = val.val() & 2;
! 			isWrite = val.val() & 1;
! 			size = (val.val()>>2)&7;
! 			count = val.val()>>5;
  			trigger = true;
  		}
***************
*** 505,509 ****
  		unsigned addr;
  		unsigned size;
! 		bool isRead;
  		bool trigger;
  
--- 511,515 ----
  		unsigned addr;
  		unsigned size;
! 		bool isRead,isWrite;
  		bool trigger;
  

Index: more_managers.cpp
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/more_managers.cpp,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** more_managers.cpp	19 Aug 2005 03:15:05 -0000	1.3
--- more_managers.cpp	23 Aug 2005 19:47:52 -0000	1.4
***************
*** 56,60 ****
  #ifdef DEBUG
  		//fprintf(stderr, "0x%08x\n", current_pc);
! 		fprintf(stderr, "0x%08x : 0x%08x\n", current_pc, iw);
  #endif
  	}
--- 56,60 ----
  #ifdef DEBUG
  		//fprintf(stderr, "0x%08x\n", current_pc);
! 		fprintf(stderr, "proc %d:: 0x%08x : 0x%08x\n", _armsim->get_procid(), current_pc, iw);
  #endif
  	}
***************
*** 80,85 ****
  	if (status==1 && !dmcu->is_busy()) {
  
! 		if (isRead)
! 			dmcu->start_read(addr, &val, size);
  		else {
  			val = mMemWrite->get_value().val();
--- 80,91 ----
  	if (status==1 && !dmcu->is_busy()) {
  
! 		if (isRead) {
! 			if (isWrite) { // swap operation
! 				val = mMemWrite->get_value().val();
! 				dmcu->start_swap(addr, &val, size);
! 			}
! 			else
! 				dmcu->start_read(addr, &val, size);
! 		}
  		else {
  			val = mMemWrite->get_value().val();
***************
*** 106,111 ****
  	if (trigger) {
  		trigger = false;
! 		_armsim->syscall_start(sc_num);
! 		busy = true;
  	}
  	else if (busy) {
--- 112,147 ----
  	if (trigger) {
  		trigger = false;
! 
! 		// interpret some specially added ones
! 		switch (sc_num) {
! 
! 			case 514:	// get processor id
! 			 	_armsim->write_gpr(0, _armsim->get_procid());
! 				break;
! 			case 515:	// get cycle count
! 				{
! 				uint64_t c = _armsim->get_cycle_count();
! 				_armsim->write_gpr(0, (uint32_t) (c));
! 				_armsim->write_gpr(1, (uint32_t) (c >> 32));
! 				break;
! 				}
! 			case 516:	// get system cycle count
! 				{
! 				uint64_t c = _armsim->get_system_cycle_count();
! 				_armsim->write_gpr(0, (uint32_t) (c));
! 				_armsim->write_gpr(1, (uint32_t) (c >> 32));
! 				break;
! 				}
! 			case 517:
! 				_armsim->set_clock_divider(_armsim->read_gpr(0));
! 				break;
! 			case 518:
! 				_armsim->sleep(_armsim->read_gpr(0));
! 				break;
! 			default:
! 				_armsim->syscall_start(sc_num);
! 				busy = true;
! 				break;
! 		}
  	}
  	else if (busy) {

Index: cache.h
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/cache.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** cache.h	21 Aug 2005 04:23:12 -0000	1.6
--- cache.h	23 Aug 2005 19:47:52 -0000	1.7
***************
*** 69,72 ****
--- 69,73 ----
  	}
  
+ 
    public:
  
***************
*** 85,93 ****
  
  		/* mask for index */
! 		index_mask = (n_block/n_assoc) - 1;
  		tag_shifts = block_bits + bsize_bits - assoc_bits;
  
  		tags = new block_t[n_block];
! 		round_robin_index = new uint16_t[n_block/n_assoc];
  	}
  
--- 86,95 ----
  
  		/* mask for index */
! 		index_mask = (n_block>>assoc_bits) - 1;
  		tag_shifts = block_bits + bsize_bits - assoc_bits;
  
  		tags = new block_t[n_block];
! 		round_robin_index = new uint16_t[n_block>>assoc_bits];
! 
  	}
  
***************
*** 99,103 ****
  	virtual void reset() {
  		memset(tags, 0, sizeof(block_t)*n_block);
! 		memset(round_robin_index, 0, sizeof(uint16_t)*n_block/n_assoc);
  	}
  
--- 101,105 ----
  	virtual void reset() {
  		memset(tags, 0, sizeof(block_t)*n_block);
! 		memset(round_robin_index, 0, (sizeof(uint16_t)*n_block)>>assoc_bits);
  	}
  
***************
*** 106,109 ****
--- 108,112 ----
  	virtual bool read(target_addr_t addr, unsigned size, uint32_t *val) = 0;
  	virtual bool write(target_addr_t addr, unsigned size, uint32_t *val) = 0;
+ 	virtual bool swap(target_addr_t addr, unsigned size, uint32_t *val) = 0;
  
  	/* to be called by biu for flushing, return the block of data */
***************
*** 182,194 ****
  	}
  
! 	/* should never call write */
  	bool write(target_addr_t addr, unsigned size, uint32_t *val) {
  		return false;
  	}
  
  	/* invalidate a line of cache */
  	bool biu_invalidate(target_addr_t addr) {
  		tag_t *blk = look_up(addr);
! 		if (!blk || !blk->valid) return false;
  		blk->valid = false;
  		return true;
--- 185,201 ----
  	}
  
! 	/* should never call write or swap*/
  	bool write(target_addr_t addr, unsigned size, uint32_t *val) {
  		return false;
  	}
  
+ 	bool swap(target_addr_t addr, unsigned size, uint32_t *val) {
+ 		return false;
+ 	}
+ 
  	/* invalidate a line of cache */
  	bool biu_invalidate(target_addr_t addr) {
  		tag_t *blk = look_up(addr);
! 		if (!blk) return false;
  		blk->valid = false;
  		return true;
***************
*** 294,299 ****
  
  			/* if the channel is busy, wait */
! 			if (biu->is_busy()) {
! 				state = PENDING_LOAD;
  			}
  			else {
--- 301,306 ----
  
  			/* if the channel is busy, wait */
! 			if (!biu->lock(this)) {
! 				state = PENDING_LOCK;
  			}
  			else {
***************
*** 338,341 ****
--- 345,352 ----
  	}
  
+ 	bool swap(target_addr_t addr, unsigned size, uint32_t *val) {
+ 		return false;
+ 	}
+ 
  	uint8_t *biu_flush(target_addr_t addr) {
  		return NULL;
***************
*** 345,350 ****
  	bool biu_invalidate(target_addr_t addr) {
  		tag_t *blk = look_up(addr);
! 		if (!blk || !blk->valid) return false;
  		blk->valid = false;
  		return true;
  	}
--- 356,367 ----
  	bool biu_invalidate(target_addr_t addr) {
  		tag_t *blk = look_up(addr);
! 		if (!blk) return false;
  		blk->valid = false;
+ 
+ 		struct data_t *line = values + (blk - tags);
+ 		if (state!=IDLE && reqLine==line) {
+ 			if (state==WAITING_LOAD) biu->unlock(this);
+ 			state = IDLE;
+ 		}
  		return true;
  	}
***************
*** 356,361 ****
  	void update_on_clock() {
  
! 		if (state==PENDING_LOAD) {
! 			if (!biu->is_busy()) {
  				biu->post_request(this, true,
  					aligned_addr, bsize, reqLine->data);
--- 373,378 ----
  	void update_on_clock() {
  
! 		if (state==PENDING_LOCK) {
! 			if (biu->lock(this)) {
  				biu->post_request(this, true,
  					aligned_addr, bsize, reqLine->data);
***************
*** 366,369 ****
--- 383,387 ----
  			reqTag->valid = true;
  			state = IDLE;
+ 			biu->unlock(this);
  		}
  	}
***************
*** 385,389 ****
  	enum {
  		IDLE,
! 		PENDING_LOAD,
  		WAITING_LOAD
  	} state;
--- 403,407 ----
  	enum {
  		IDLE,
! 		PENDING_LOCK,
  		WAITING_LOAD
  	} state;
***************
*** 460,534 ****
  
  		reqTag = look_up(addr);
! 		if (!reqTag) {
! 
! 
! 			nReadMisses++;
  
- 			/* read the block in */
- 			reqTag = allocate_block(addr);
  			reqLine = values + (reqTag - tags);
  
! 			aligned_addr = addr>>bsize_bits << bsize_bits;
! 
! 			// need to flush this line
! 			if (reqTag->valid && reqLine->dirty) {
  
! 				// get the address of the line
! 				target_addr_t flush_index = (reqTag-tags)/n_assoc;
! 				flush_addr = get_address(flush_index, reqTag->tag);
  
! 				// if the channel is busy, wait */
! 				if (biu->is_busy()) {
! 					state = PENDING_FLUSH;
! 				}
! 				else {
! 					biu->post_request(this, false,
! 						flush_addr, bsize, reqLine->data);
! 					state = WAITING_FLUSH;
! 				}
! 			}
! 			else {
! 				reqLine->dirty = false;
! 				// if the channel is busy, wait */
! 				if (biu->is_busy()) {
! 					state = PENDING_LOAD;
! 				}
! 				else {
! 					biu->post_request(this, true,
! 						aligned_addr, bsize, reqLine->data);
! 					state = WAITING_LOAD;
! 				}
! 			}
  
! 			reqTag->tag = get_tag(addr);
  
  			return false;
  		}
  
- 		reqLine = values + (reqTag - tags);
- 		uint8_t *ptr = reqLine->data + (addr&(bsize-1));
- 
- 		if (size==4)
- #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN
- 			*val = swap_word(*reinterpret_cast<uint32_t *>(ptr));
- #else 
-             *val = *reinterpret_cast<uint32_t *>(ptr);
- #endif
- 		else if (size==1)
- 			*val = *ptr;
- 		else if (size==2)
- #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN
- 			*val = swap_half_word(*reinterpret_cast<uint16_t *>(ptr));
- #else 
- 			*val = *reinterpret_cast<uint16_t *>(ptr);
- #endif
- 		else {
- 			fprintf(stderr, "%s: illegal access size, must be 1, 2 or 4 - "
- 							"addr=%08x size=%d\n", name.c_str(), addr, size);
- 			exit(1);
- 		}
- 
- 		nReads++;
- 		return true;
  	}
  
--- 478,500 ----
  
  		reqTag = look_up(addr);
! 		if (reqTag) {
  
  			reqLine = values + (reqTag - tags);
+ 			uint8_t *ptr = reqLine->data + (addr&(bsize-1));
+ 			read_content(ptr, addr, size, val);
  
! 			nReads++;
  
! 			return true;
! 		}
! 		else {
  
! 			nReadMisses++;
  
! 			flush_and_load(addr);
  
  			return false;
  		}
  
  	}
  
***************
*** 552,577 ****
  			reqLine->dirty = true; // dirty line now
  
! 			uint8_t *ptr = reqLine->data + addr%bsize;
! 
! 			/* swap the value if necessary */
! 			if (size==4)
! #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN
! 				*reinterpret_cast<uint32_t *>(ptr) = swap_word(*val);
! #else
! 				*reinterpret_cast<uint32_t *>(ptr) = *val;
! #endif
! 			else if (size==1)
! 				*ptr = (uint8_t)(*val);
! 			else if (size==2)
! #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN
! 				*reinterpret_cast<uint16_t *>(ptr) =
! 					swap_half_word((uint16_t)*val);
! #else
! 				*reinterpret_cast<uint16_t *>(ptr) = (uint16_t)*val;
! #endif
! 			else 
! 				fprintf(stderr, "%s: illegal access size, must be 1, 2 or 4 - "
! 							"addr=%08x size=%d\n", name.c_str(), addr, size);
  
  			nWrites++;
  
--- 518,524 ----
  			reqLine->dirty = true; // dirty line now
  
! 			uint8_t *ptr = reqLine->data + (addr&(bsize-1));
  
+ 			write_content(ptr, addr, size, val);
  			nWrites++;
  
***************
*** 586,626 ****
  			nWriteMisses++;
  
! 			// remember the address
! 			aligned_addr = addr>>bsize_bits<<bsize_bits;
  
- 			/* locate a block */
- 			reqTag = allocate_block(addr);
  			reqLine = values + (reqTag - tags);
  
! 			// need to flush this line
! 			if (reqTag->valid && reqLine->dirty) {
  
! 				// get the address of the line
! 				target_addr_t flush_index = (reqTag-tags)/n_assoc;
! 				flush_addr = get_address(flush_index, reqTag->tag);
  
! 				// wait for biu
! 				if (biu->is_busy()) {
! 					state = PENDING_FLUSH;
! 				}
! 				else {
! 					biu->post_request(this,
! 						false, flush_addr, bsize, reqLine->data);
! 					state = WAITING_FLUSH;
! 				}
! 			}
! 			else { // need to load the line
! 				reqLine->dirty = false;
! 				if (biu->is_busy()) {
! 					state = PENDING_LOAD;
! 				}
! 				else {
! 					biu->post_request(this,
! 						true, aligned_addr, bsize, reqLine->data);
! 					state = WAITING_LOAD;
! 				}
  			}
  
! 			reqTag->tag = get_tag(addr);
  
  			return false;
--- 533,585 ----
  			nWriteMisses++;
  
! 			flush_and_load(addr);
! 
! 			return false;
! 		}
! 	}
! 
! 	bool swap(target_addr_t addr, unsigned size, uint32_t *val) {
! 
! 		/* if cache busy, cannot do anything */
! 		if (state!=IDLE) return false;
! 
! 		/* check that this is not across cache line boundary */
! 		if ((addr>>bsize_bits)!=((addr+size-1)>>bsize_bits)) {
! 			fprintf(stderr, "%s: illegal access crosses line boundary - "
! 							"addr=%08x size=%d\n", name.c_str(), addr, size);
! 			exit(1);
! 		}
! 
! 		/* if in cache, then update the cache line with data */
! 		reqTag = look_up(addr);
! 		if (reqTag) {
  
  			reqLine = values + (reqTag - tags);
  
! 			uint8_t *ptr = reqLine->data + addr%bsize;
! 			uint32_t rval;
  
! 			read_content(ptr, addr, size, &rval);
! 			write_content(ptr, addr, size, val);
  
! 			nWrites++;
! 			nReads++;
! 
! 			/* notify the write so that others can invalidate their stale data
! 			   in a SMP configuration */
! 			if (rval!=*val) {// do not notify too frequently for spin locks
! 				biu->notify_write(this, addr);
! 				reqLine->dirty = true; // dirty line now
  			}
  
! 			*val = rval;
! 			return true;
! 		}
! 		else {
! 
! 			nWriteMisses++;
! 			nReadMisses++;
! 
! 			flush_and_load(addr);
  
  			return false;
***************
*** 636,641 ****
  
  			// if pending to flush this line, can skip waiting
! 			if (state==PENDING_FLUSH && reqLine==line) {
! 				state = PENDING_LOAD;
  			}
  
--- 595,602 ----
  
  			// if pending to flush this line, can skip waiting
! 			// since this only happens when another cache is loading this line,
! 			// this cache cannot be holding the biu lock
! 			if (state==PENDING_LOCK_FLUSH && reqLine==line) {
! 				state = PENDING_LOCK_LOAD;
  			}
  
***************
*** 651,662 ****
  	bool biu_invalidate(target_addr_t addr) {
  
! 		tag_t *blk = look_up(addr);
  
! 		if (!blk || !blk->valid) return false;
  	
! 		struct data_t *line = values + (blk - tags);
! 		// this state should not occur
! 		assert (!(state==PENDING_FLUSH && reqLine==line));
! 		blk->valid = false;
  		return true;
  	}
--- 612,631 ----
  	bool biu_invalidate(target_addr_t addr) {
  
! 		tag_t *tag = look_up(addr);
  
! 		if (!tag) {
! 			return false;
! 		}
  	
! 		tag->valid = false;
! 
! 		// if loading this line, abort action
! 		struct data_t *line = values + (tag - tags);
! 		if (state!=IDLE && reqLine==line) {
! 			if (state==WAITING_FLUSH || state==WAITING_LOAD)
! 				biu->unlock(this);
! 			state = IDLE;
! 		}
! 
  		return true;
  	}
***************
*** 666,670 ****
  		if (tag) {
  			struct data_t *line = values + (tag - tags);
! 			return line ->dirty;
  		}
  		return false;
--- 635,639 ----
  		if (tag) {
  			struct data_t *line = values + (tag - tags);
! 			return line->dirty;
  		}
  		return false;
***************
*** 675,680 ****
  		switch (state) {
  
! 			case PENDING_FLUSH: 
! 				if (!biu->is_busy()) {
  					biu->post_request(this,
  						false, flush_addr, bsize, reqLine->data);
--- 644,650 ----
  		switch (state) {
  
! 			case PENDING_LOCK_FLUSH: 
! 				if (biu->lock(this)) {
! 					reqLine->dirty = false;
  					biu->post_request(this,
  						false, flush_addr, bsize, reqLine->data);
***************
*** 685,695 ****
  			case WAITING_FLUSH:
  				if (biu->get_ack(this)) {
! 					reqLine->dirty = false;
! 					state = PENDING_LOAD;
  				}
  				// fall through here
  
! 			case PENDING_LOAD:
! 				if (!biu->is_busy()) {
  					biu->post_request(this, true,
  						aligned_addr, bsize, reqLine->data);
--- 655,673 ----
  			case WAITING_FLUSH:
  				if (biu->get_ack(this)) {
! 					reqTag->valid = true;
! 					reqTag->tag = get_tag(aligned_addr);
! 					biu->post_request(this, true,
! 						aligned_addr, bsize, reqLine->data);
! 					state = WAITING_LOAD;
  				}
+ 				break;
  				// fall through here
  
! 			case PENDING_LOCK_LOAD:
! 				if (biu->lock(this)) {
! 					// make valid bit true once starting to load
! 					// so that it can be invalidated if other modifies the line
! 					reqTag->valid = true;
! 					reqTag->tag = get_tag(aligned_addr);
  					biu->post_request(this, true,
  						aligned_addr, bsize, reqLine->data);
***************
*** 701,705 ****
  				if (biu->get_ack(this)) {
  					state = IDLE;
! 					reqTag->valid = true;
  				}
  				break;
--- 679,683 ----
  				if (biu->get_ack(this)) {
  					state = IDLE;
! 					biu->unlock(this);
  				}
  				break;
***************
*** 732,739 ****
  	enum {
  		IDLE,
! 		PENDING_FLUSH,
! 		WAITING_FLUSH,
! 		PENDING_LOAD,
! 		WAITING_LOAD
  	} state;
  
--- 710,717 ----
  	enum {
  		IDLE,
! 		PENDING_LOCK_FLUSH,	// waiting for lock to flush
! 		WAITING_FLUSH,		// waiting for flush to finish
! 		PENDING_LOCK_LOAD,	// waiting for lock to load	
! 		WAITING_LOAD		// waiting for load to finish
  	} state;
  
***************
*** 744,747 ****
--- 722,823 ----
  	struct data_t *reqLine;
  	struct data_t *values; //[n_block/n_assoc][n_assoc];
+ 
+ 
+   private:
+ 
+ 	void read_content(uint8_t *ptr, target_addr_t addr,
+ 		unsigned size, uint32_t *val) {
+ 
+ 		if (size==4)
+ #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN
+ 			*val = swap_word(*reinterpret_cast<uint32_t *>(ptr));
+ #else 
+             *val = *reinterpret_cast<uint32_t *>(ptr);
+ #endif
+ 		else if (size==1)
+ 			*val = *ptr;
+ 		else if (size==2)
+ #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN
+ 			*val = swap_half_word(*reinterpret_cast<uint16_t *>(ptr));
+ #else 
+ 			*val = *reinterpret_cast<uint16_t *>(ptr);
+ #endif
+ 		else {
+ 			fprintf(stderr, "%s: illegal access size, must be 1, 2 or 4 - "
+ 							"addr=%08x size=%d\n", name.c_str(), addr, size);
+ 			exit(1);
+ 		}
+ 	}
+ 	
+ 	void write_content(uint8_t *ptr, target_addr_t addr,
+ 		unsigned size, uint32_t *val) {
+ 
+ 		/* swap the value if necessary */
+ 		if (size==4)
+ #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN
+ 			*reinterpret_cast<uint32_t *>(ptr) = swap_word(*val);
+ #else
+ 			*reinterpret_cast<uint32_t *>(ptr) = *val;
+ #endif
+ 		else if (size==1)
+ 			*ptr = (uint8_t)(*val);
+ 		else if (size==2)
+ #if WORDS_BIGENDIAN==TARGET_LITTLE_ENDIAN
+ 			*reinterpret_cast<uint16_t *>(ptr) =
+ 				swap_half_word((uint16_t)*val);
+ #else
+ 			*reinterpret_cast<uint16_t *>(ptr) = (uint16_t)*val;
+ #endif
+ 		else 
+ 			fprintf(stderr, "%s: illegal access size, must be 1, 2 or 4 - "
+ 						"addr=%08x size=%d\n", name.c_str(), addr, size);
+ 	}
+ 
+ 
+ 	void flush_and_load(target_addr_t addr) {
+ 
+ 		/* read the block in */
+ 		reqTag = allocate_block(addr);
+ 		reqLine = values + (reqTag - tags);
+ 
+ 		aligned_addr = addr>>bsize_bits << bsize_bits;
+ 
+ 		// need to flush this line
+ 		if (reqTag->valid && reqLine->dirty) {
+ 
+ 			// get the address of the line
+ 			target_addr_t flush_index = (reqTag-tags)>>assoc_bits;
+ 			flush_addr = get_address(flush_index, reqTag->tag);
+ 
+ 			// if the channel is busy, wait */
+ 			if (!biu->lock(this)) {
+ 				state = PENDING_LOCK_FLUSH;
+ 			}
+ 			else {
+ 				reqTag->valid = false;
+ 				biu->post_request(this, false,
+ 					flush_addr, bsize, reqLine->data);
+ 				state = WAITING_FLUSH;
+ 			}
+ 		}
+ 		else {
+ 			reqTag->valid = false;
+ 			// if the channel is busy, wait */
+ 			if (!biu->lock(this)) {
+ 				state = PENDING_LOCK_LOAD;
+ 			}
+ 			else {
+ 				// make valid bit true once starting to load
+ 				// so that it can be invalidated if other modifies the line
+ 				reqTag->valid = true;
+ 				reqTag->tag = get_tag(aligned_addr);
+ 				biu->post_request(this, true,
+ 					aligned_addr, bsize, reqLine->data);
+ 				state = WAITING_LOAD;
+ 			}
+ 		}
+ 
+ 	}
+ 
  };
  

Index: armsim.cpp
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.cpp,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** armsim.cpp	21 Aug 2005 04:23:12 -0000	1.7
--- armsim.cpp	23 Aug 2005 19:47:52 -0000	1.8
***************
*** 66,69 ****
--- 66,70 ----
  	mNewPC->connect(mRF);
  	mSC->set_armsim(this);
+ 	mIF->set_armsim(this);
  	mCoProc->set_armsim(this);
  
***************
*** 79,82 ****
--- 80,86 ----
  
  	syscall_buf = NULL;
+ 
+ 	c_div = 1;
+ 	c_count = 0;
  	
  	/* reset every thing */
***************
*** 152,155 ****
--- 156,161 ----
  		work_it = work_list.erase(work_it);
  	}
+ 
+ 	c_count = 0;
  }
  
***************
*** 228,231 ****
--- 234,239 ----
  #endif
  
+   if (c_count==0) {
+ 
  	/** Activate all OSMs in order. */
  	for (work_it=work_list.begin(); work_it!=work_list.end();) {
***************
*** 272,280 ****
  	mSC->update_on_clock();
  
- 	imcu->update_on_clock();
- 	dmcu->update_on_clock();
- 	biu->update_on_clock();
- 
  	syscall_update();
  }
  
--- 280,297 ----
  	mSC->update_on_clock();
  
  	syscall_update();
+ 
+ 	c_count = c_div;
+   }
+ 
+   c_count--;
+   system_cycle_count++;
+ 
+   // memory operates at normal speed otherwise bus will be clogged
+   imcu->update_on_clock();
+   dmcu->update_on_clock();
+ 
+   if (use_self_mem) biu->update_on_clock();
+ 
  }
  
***************
*** 440,441 ****
--- 457,470 ----
  }
  
+ 
+ void arm_simulator::clone_states(arm_simulator *sim)
+ {
+ 	for (unsigned ii=0; ii<16; ii++)
+ 		write_gpr(ii, sim->read_gpr(ii));
+ 
+ 	write_cpsr(sim->read_cpsr());
+ 
+ 	/* set brk point for syscall interpretation. */
+ 	syscall_set_brk(sim->syscall_get_brk());
+ 	syscall_set_mmap_brk(sim->syscall_get_mmap_brk());
+ }

Index: Makefile.am
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/Makefile.am,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** Makefile.am	21 Aug 2005 04:23:12 -0000	1.5
--- Makefile.am	23 Aug 2005 19:47:52 -0000	1.6
***************
*** 20,24 ****
  
  libarmsim_a_SOURCES = define.cpp machines.cpp \
! 		main.cpp armsim.cpp more_managers.cpp \
  		ext_func.cpp fetch_oper_dec.cpp biu.cpp \
  		mang_list.hpp armsim.hpp \
--- 20,24 ----
  
  libarmsim_a_SOURCES = define.cpp machines.cpp \
! 		armsim.cpp more_managers.cpp \
  		ext_func.cpp fetch_oper_dec.cpp biu.cpp \
  		mang_list.hpp armsim.hpp \

Index: fetch_oper_pat.hpp
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/fetch_oper_pat.hpp,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** fetch_oper_pat.hpp	19 Aug 2005 03:15:05 -0000	1.5
--- fetch_oper_pat.hpp	23 Aug 2005 19:47:52 -0000	1.6
***************
*** 3,19 ****
  
  Input statistics 
! Total entries  : 1284
! Unique labels  : 550
! Shannon entropy     : 9.10075
! Huffman tree height : 9.13662
  
  Decoder characteristics 
  Gamma          : 0.25
  1 bit only     : 0
[...3476 lines suppressed...]
!    _FUNC_CALL(DEC_fetch_oper_unknown);
   }
  }
--- 5304,5319 ----
  _STUB_ENTRY(stub_0_20)
  {
!  if _PATTERN_TRUE(0x00000f60, 0x00000000) {
!    if _PATTERN_TRUE(0x00000090, 0x00000090) {
!      _FUNC_CALL(DEC_fetch_oper_swapb_);
!    } else {
!      _FUNC_CALL(DEC_fetch_oper_unknown);
!    }
   } else {
!    if _PATTERN_TRUE(0x00000090, 0x00000090) {
!      _FUNC_CALL(DEC_fetch_oper_store_ext_imm_mem_mode_6_);
!    } else {
!      _FUNC_CALL(DEC_fetch_oper_unknown);
!    }
   }
  }

Index: main.cpp
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/main.cpp,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** main.cpp	21 Aug 2005 04:23:12 -0000	1.6
--- main.cpp	23 Aug 2005 19:47:52 -0000	1.7
***************
*** 93,99 ****
  	if(prog_name)
  	{
! 		memory *mem = new memory();
! 		bus_interface *biu = 
! 			new bus_interface("biu", mem, n_mem_rlat, n_mem_wlat);
  
  		sima = new arm_simulator(verbose, need_fpe, true,
--- 93,99 ----
  	if(prog_name)
  	{
! 	//	memory *mem = new memory();
! 	//	bus_interface *biu = 
! 	//		new bus_interface("biu", mem, n_mem_rlat, n_mem_wlat);
  
  		sima = new arm_simulator(verbose, need_fpe, true,
***************
*** 102,106 ****
  			n_itlb_blk, n_itlb_assoc, n_itlb_psize,
  			n_dtlb_blk, n_dtlb_assoc, n_dtlb_psize, n_tlb_lat,
! 			mem, biu);
  
  		signal(SIGUSR1, sig_handler);
--- 102,106 ----
  			n_itlb_blk, n_itlb_assoc, n_itlb_psize,
  			n_dtlb_blk, n_dtlb_assoc, n_dtlb_psize, n_tlb_lat,
! 			NULL, NULL);
  
  		signal(SIGUSR1, sig_handler);
***************
*** 120,123 ****
--- 120,124 ----
  #endif
  
+ 		sima->set_procid(0);
  		sima->run(max_cnum);
  
***************
*** 143,148 ****
  
  		delete sima;
! 		delete biu;
! 		delete mem;
  	}
  	else usage(argv[0]);
--- 144,149 ----
  
  		delete sima;
! 	//	delete biu;
! 	//	delete mem;
  	}
  	else usage(argv[0]);

Index: machines.cpp
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/machines.cpp,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** machines.cpp	19 Aug 2005 03:15:05 -0000	1.6
--- machines.cpp	23 Aug 2005 19:47:52 -0000	1.7
***************
*** 70,73 ****
--- 70,74 ----
  #define V_store_ext_reg_m_size C_12
  #define V_swap_coding C_3
+ #define V_swapb_coding C_3
  #define V_ldm_syn C_14
  #define V_ldm_coding C_6
***************
*** 5277,5281 ****
  
  
[...6361 lines suppressed...]
  &__act_L_$S_ID$38430,
! &__act_L_$S_EX$38431,
! &__act_L_$S_BF$38433,
  };
  
--- 46625,46638 ----
  &__act_L_$S_WB$38100,
  &__act_L_$S_ID$38150,
+ &__act_L_$S_EX$38151,
+ &__act_L_$S_BF$38153,
+ &__act_L_$S_WB$38170,
  &__act_L_$S_ID$38220,
  &__act_L_$S_ID$38290,
  &__act_L_$S_ID$38360,
  &__act_L_$S_ID$38430,
! &__act_L_$S_ID$38500,
! &__act_L_$S_EX$38501,
! &__act_L_$S_BF$38503,
  };
  

Index: armsim.hpp
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.hpp,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** armsim.hpp	21 Aug 2005 04:23:12 -0000	1.5
--- armsim.hpp	23 Aug 2005 19:47:52 -0000	1.6
***************
*** 128,131 ****
--- 128,132 ----
  	/* get the number of cycles */
  	uint64_t get_cycle_count() const {return cycle_count;}
+ 	uint64_t get_system_cycle_count() const {return system_cycle_count;}
  
  
***************
*** 217,220 ****
--- 218,237 ----
      unsigned syscall_mem_size;
  
+ 	/* a few routines for smp support */
+ 
+ 	// initialize registers
+ 	void clone_states(arm_simulator *);
+ 
+ 	// clock divider
+ 	void set_clock_divider(unsigned c) {c_div=c_count=c;}
+ 
+ 	// sleep for c cycles
+ 	void sleep(unsigned c) {c_count=c_div+c;}
+ 
+ 	// get the id of the processor
+ 	void set_procid(unsigned id) {procid = id;}
+ 	unsigned get_procid() const {return procid;}
+ 
+ 
    private:
      /* context for system call interpretation */
***************
*** 243,246 ****
--- 260,264 ----
  	bool emu_syscall;
  
+ 	/* create biu and mem myself? */
  	bool use_self_mem;
  
***************
*** 250,254 ****
  	enum status_t status;
  
! 	uint64_t cycle_count;	/* number of simulation cycles*/
  
  	std::list<_opt_machine_ *> work_list;
--- 268,275 ----
  	enum status_t status;
  
! 	unsigned procid;
! 	uint64_t cycle_count;		/* number of simulation cycles, divided*/
! 	uint64_t system_cycle_count;/* number of undivided cycles */
! 	unsigned c_div, c_count;
  
  	std::list<_opt_machine_ *> work_list;

Index: mcu.hpp
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/mcu.hpp,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** mcu.hpp	19 Aug 2005 03:15:05 -0000	1.1
--- mcu.hpp	23 Aug 2005 19:47:52 -0000	1.2
***************
*** 37,41 ****
  		assert(state==IDLE);
  
! 		buf_read = true;
  		buf_val_ptr = val;
  		buf_size = size;
--- 37,41 ----
  		assert(state==IDLE);
  
! 		buf_mode = MCU_READ;
  		buf_val_ptr = val;
  		buf_size = size;
***************
*** 51,55 ****
  		assert(state==IDLE);
  
! 		buf_read = false;
  		buf_val_ptr = val;
  		buf_size = size;
--- 51,55 ----
  		assert(state==IDLE);
  
! 		buf_mode = MCU_WRITE;
  		buf_val_ptr = val;
  		buf_size = size;
***************
*** 61,64 ****
--- 61,78 ----
  	}
  	
+ 	void start_swap(target_addr_t addr, uint32_t *val, unsigned size) {
+ 
+ 		assert(state==IDLE);
+ 
+ 		buf_mode = MCU_SWAP;
+ 		buf_val_ptr = val;
+ 		buf_size = size;
+ 		buf_addr = addr;
+ 		buf_blk_ptr = NULL;
+ 
+ 		state = WAITING_TLB;
+ 		update();
+ 	}
+ 
  	// Read an array of bytes from memory
  	void start_read_block(target_addr_t addr, uint8_t *ptr, unsigned size) {
***************
*** 67,71 ****
  		assert(ptr);
  
! 		buf_read = true;
  		buf_size = size;
  		buf_addr = addr;
--- 81,85 ----
  		assert(ptr);
  
! 		buf_mode = MCU_READ;
  		buf_size = size;
  		buf_addr = addr;
***************
*** 81,85 ****
  		assert(ptr);
  
! 		buf_read = false;
  		buf_size = size;
  		buf_addr = addr;
--- 95,99 ----
  		assert(ptr);
  
! 		buf_mode = MCU_WRITE;
  		buf_size = size;
  		buf_addr = addr;
***************
*** 112,117 ****
  
  			if (buf_blk_ptr==NULL) {
! 				if (buf_read && cash->read(buf_addr, buf_size, buf_val_ptr) ||
! 					!buf_read && cash->write(buf_addr, buf_size, buf_val_ptr))
  				state = IDLE;
  			}
--- 126,135 ----
  
  			if (buf_blk_ptr==NULL) {
! 				if (buf_mode==MCU_READ &&
! 						cash->read(buf_addr, buf_size, buf_val_ptr) ||
! 					buf_mode==MCU_WRITE &&
! 						cash->write(buf_addr, buf_size, buf_val_ptr) ||
! 					buf_mode==MCU_SWAP &&
! 						cash->swap(buf_addr, buf_size, buf_val_ptr))
  				state = IDLE;
  			}
***************
*** 120,124 ****
  				uint32_t val;
  
! 				if (buf_read && cash->read(buf_addr, 1, &val)) {
  					*buf_blk_ptr = (uint8_t)val;
  					buf_blk_ptr++;
--- 138,142 ----
  				uint32_t val;
  
! 				if (buf_mode==MCU_READ && cash->read(buf_addr, 1, &val)) {
  					*buf_blk_ptr = (uint8_t)val;
  					buf_blk_ptr++;
***************
*** 126,130 ****
  					buf_size--;
  				}
! 				else if (!buf_read) {
  		
  					val = *buf_blk_ptr;
--- 144,148 ----
  					buf_size--;
  				}
! 				else if (buf_mode==MCU_WRITE) {
  		
  					val = *buf_blk_ptr;
***************
*** 153,157 ****
  
  	/* buffered request information */
! 	bool buf_read; // is read?
  	uint32_t *buf_val_ptr;
  	unsigned buf_size;
--- 171,180 ----
  
  	/* buffered request information */
! 	enum {
! 		MCU_READ,
! 		MCU_WRITE,
! 		MCU_SWAP
! 	} buf_mode; // is read?
! 
  	uint32_t *buf_val_ptr;
  	unsigned buf_size;

Index: fetch_oper_tab.hpp
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/fetch_oper_tab.hpp,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** fetch_oper_tab.hpp	19 Aug 2005 03:15:05 -0000	1.3
--- fetch_oper_tab.hpp	23 Aug 2005 19:47:52 -0000	1.4
***************
*** 3691,3699 ****
  }
  
  unsigned DEC_fetch_oper_ldm_update_rn_(_INST_T inst) {
  #ifdef _DUMP_DECODE
  std::cerr << "ldm_update_rn_" << std::endl;
  #endif
!   return 527;
  }
  
--- 3691,3706 ----
  }
  
+ unsigned DEC_fetch_oper_swapb_(_INST_T inst) {
+ #ifdef _DUMP_DECODE
+ std::cerr << "swapb_" << std::endl;
+ #endif
+   return 527;
+ }
+ 
  unsigned DEC_fetch_oper_ldm_update_rn_(_INST_T inst) {
  #ifdef _DUMP_DECODE
  std::cerr << "ldm_update_rn_" << std::endl;
  #endif
!   return 528;
  }
  
***************
*** 3702,3706 ****
  std::cerr << "ldm_noupdate_rn_" << std::endl;
  #endif
!   return 528;
  }
  
--- 3709,3713 ----
  std::cerr << "ldm_noupdate_rn_" << std::endl;
  #endif
!   return 529;
  }
  
***************
*** 3709,3713 ****
  std::cerr << "stm_update_rn_" << std::endl;
  #endif
!   return 529;
  }
  
--- 3716,3720 ----
  std::cerr << "stm_update_rn_" << std::endl;
  #endif
!   return 530;
  }
  
***************
*** 3716,3720 ****
  std::cerr << "stm_noupdate_rn_" << std::endl;
  #endif
!   return 530;
  }
  
--- 3723,3727 ----
  std::cerr << "stm_noupdate_rn_" << std::endl;
  #endif
!   return 531;
  }
  
***************
*** 3723,3727 ****
  std::cerr << "mult_mla_" << std::endl;
  #endif
!   return 531;
  }
  
--- 3730,3734 ----
  std::cerr << "mult_mla_" << std::endl;
  #endif
!   return 532;
  }
  
***************
*** 3730,3734 ****
  std::cerr << "mult_mlas_" << std::endl;
  #endif
!   return 532;
  }
  
--- 3737,3741 ----
  std::cerr << "mult_mlas_" << std::endl;
  #endif
!   return 533;
  }
  
***************
*** 3737,3741 ****
  std::cerr << "mult_mul_" << std::endl;
  #endif
!   return 533;
  }
  
--- 3744,3748 ----
  std::cerr << "mult_mul_" << std::endl;
  #endif
!   return 534;
  }
  
***************
*** 3744,3748 ****
  std::cerr << "mult_muls_" << std::endl;
  #endif
!   return 534;
  }
  
--- 3751,3755 ----
  std::cerr << "mult_muls_" << std::endl;
  #endif
!   return 535;
  }
  
***************
*** 3751,3755 ****
  std::cerr << "mult_long_smull_" << std::endl;
  #endif
!   return 535;
  }
  
--- 3758,3762 ----
  std::cerr << "mult_long_smull_" << std::endl;
  #endif
!   return 536;
  }
  
***************
*** 3758,3762 ****
  std::cerr << "mult_long_smulls_" << std::endl;
  #endif
!   return 536;
  }
  
--- 3765,3769 ----
  std::cerr << "mult_long_smulls_" << std::endl;
  #endif
!   return 537;
  }
  
***************
*** 3765,3769 ****
  std::cerr << "mult_long_smlal_" << std::endl;
  #endif
!   return 537;
  }
  
--- 3772,3776 ----
  std::cerr << "mult_long_smlal_" << std::endl;
  #endif
!   return 538;
  }
  
***************
*** 3772,3776 ****
  std::cerr << "mult_long_smlals_" << std::endl;
  #endif
!   return 538;
  }
  
--- 3779,3783 ----
  std::cerr << "mult_long_smlals_" << std::endl;
  #endif
!   return 539;
  }
  
***************
*** 3779,3783 ****
  std::cerr << "mult_long_umull_" << std::endl;
  #endif
!   return 539;
  }
  
--- 3786,3790 ----
  std::cerr << "mult_long_umull_" << std::endl;
  #endif
!   return 540;
  }
  
***************
*** 3786,3790 ****
  std::cerr << "mult_long_umulls_" << std::endl;
  #endif
!   return 540;
  }
  
--- 3793,3797 ----
  std::cerr << "mult_long_umulls_" << std::endl;
  #endif
!   return 541;
  }
  
***************
*** 3793,3797 ****
  std::cerr << "mult_long_umlal_" << std::endl;
  #endif
!   return 541;
  }
  
--- 3800,3804 ----
  std::cerr << "mult_long_umlal_" << std::endl;
  #endif
!   return 542;
  }
  
***************
*** 3800,3804 ****
  std::cerr << "mult_long_umlals_" << std::endl;
  #endif
!   return 542;
  }
  
--- 3807,3811 ----
  std::cerr << "mult_long_umlals_" << std::endl;
  #endif
!   return 543;
  }
  
***************
*** 3807,3811 ****
  std::cerr << "syscall_" << std::endl;
  #endif
!   return 543;
  }
  
--- 3814,3818 ----
  std::cerr << "syscall_" << std::endl;
  #endif
!   return 544;
  }
  
***************
*** 3814,3818 ****
  std::cerr << "coproc_inst_cdp_" << std::endl;
  #endif
!   return 544;
  }
  
--- 3821,3825 ----
  std::cerr << "coproc_inst_cdp_" << std::endl;
  #endif
!   return 545;
  }
  
***************
*** 3821,3825 ****
  std::cerr << "coproc_inst_mcr_" << std::endl;
  #endif
!   return 545;
  }
  
--- 3828,3832 ----
  std::cerr << "coproc_inst_mcr_" << std::endl;
  #endif
!   return 546;
  }
  
***************
*** 3828,3832 ****
  std::cerr << "coproc_inst_mrc_" << std::endl;
  #endif
!   return 546;
  }
  
--- 3835,3839 ----
  std::cerr << "coproc_inst_mrc_" << std::endl;
  #endif
!   return 547;
  }
  
***************
*** 3835,3839 ****
  std::cerr << "coproc_inst_ldc_" << std::endl;
  #endif
!   return 547;
  }
  
--- 3842,3846 ----
  std::cerr << "coproc_inst_ldc_" << std::endl;
  #endif
!   return 548;
  }
  
***************
*** 3842,3846 ****
  std::cerr << "coproc_inst_stc_" << std::endl;
  #endif
!   return 548;
  }
  
--- 3849,3853 ----
  std::cerr << "coproc_inst_stc_" << std::endl;
  #endif
!   return 549;
  }
  
***************
*** 3849,3853 ****
  std::cerr << "unknown" << std::endl;
  #endif
!   return 549;
  }
  
--- 3856,3860 ----
  std::cerr << "unknown" << std::endl;
  #endif
!   return 550;
  }
  

Index: biu.cpp
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/biu.cpp,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** biu.cpp	21 Aug 2005 04:23:12 -0000	1.1
--- biu.cpp	23 Aug 2005 19:47:52 -0000	1.2
***************
*** 13,17 ****
  	vector<cache *>::iterator cit;
  	for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) {
! 		if ((*cit)->is_block_dirty(addr)) {
  			uint8_t *pval = (*cit)->biu_flush(addr);
  			if (pval) { // flush occurs
--- 13,17 ----
  	vector<cache *>::iterator cit;
  	for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) {
! 		if (*cit!=cash && (*cit)->is_block_dirty(addr)) {
  			uint8_t *pval = (*cit)->biu_flush(addr);
  			if (pval) { // flush occurs
***************
*** 31,35 ****
  	vector<cache *>::iterator cit;
  	for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) {
! 		(*cit)->biu_invalidate(addr);
  	}
  }
--- 31,35 ----
  	vector<cache *>::iterator cit;
  	for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) {
! 		if (*cit!=cash) (*cit)->biu_invalidate(addr);
  	}
  }

--- NEW FILE: biu.h ---

#ifndef __BUI_H__
#define __BUI_H__

#include <cstdio>
#include <string>
#include "misc.h"

#include <vector>
#include <cassert>

namespace simulator {

class cache;

class bus_interface {

	public:

		bus_interface(const std::string& name, emulator::memory *mem,
			unsigned r_latency, unsigned w_latency,
			bool smp=false) :
			name(name), mem(mem),
			read_latency(r_latency), write_latency(w_latency), smp(smp) {

			assert(read_latency>0);
			assert(write_latency>0);
			reset();
		}

		void reset() {
			naccess=nbusy=nfree=0;
			ack = false;
			delay = 0;
			owner = NULL;
		}

		void post_request(cache *cash, bool read, target_addr_t addr,
			unsigned size, void *ptr) {

			assert(owner==cash);
			naccess++;
			delay = read?read_latency:write_latency;
			ack = false;

			if (smp && read) {
				// if a read, need to check if data dirty in some cache
				// if a write, do nothing special
				smp_service_read(cash, addr, size, ptr);
			}
			else {
				if (read) mem->read_block(ptr, addr, size);
				else mem->write_block(addr, ptr, size);
			}

			return;
		}

		// get acknowledgement and clears ack bit
		bool get_ack(cache *cash) {

			assert(cash==owner);
			bool oldack = ack;
			ack = false;
			return oldack;
		}

		bool lock(cache *cash) {

			// if free then good
			if (owner==NULL) {
				owner = cash;
				return true;
			}
			return false;
		}

		void unlock(cache *cash) {

			assert(owner==cash);
			owner = NULL;
		}

		void update_on_clock() {

			if (delay>0) {
				if (delay==1) ack = true;
				--delay;
				nbusy++;
			}
			else {
				nfree++;
			}
		}

		void print_stats(FILE *fp) {
			fprintf(fp, "Total %s accesses: ", name.c_str());
			dump_int64(naccess, fp);
			fprintf(fp, "\n%s activity:	   %.3f%%\n",
				name.c_str(), 100.0*nbusy/(nbusy+nfree));
		}

		void notify_write(cache *c, target_addr_t addr) {
			if (smp) {
				smp_service_write(c, addr);
			}
			return;
		}

		void register_icache(cache *c) {
			icaches.push_back(c);
		}

		void register_dcache(cache *c) {
			dcaches.push_back(c);
		}

	private:

		const std::string name;
		const unsigned read_latency;
		const unsigned write_latency;
		const bool smp;	// smp support

		emulator::memory *mem;

		uint64_t naccess;
		uint64_t nbusy;	/*busy cycles*/
		uint64_t nfree;	/*free cycles*/

		bool ack;
		uint32_t delay;

		cache *owner;
		std::vector<cache *> icaches;
		std::vector<cache *> dcaches;

		void smp_service_read(cache *, target_addr_t, unsigned, void *);
		void smp_service_write(cache *, target_addr_t);
};

}

#endif