[Simit-arm-cvs] simit-arm/simulator biu.cpp,NONE,1.1 Makefile.am,1.4,1.5 armsim.cpp,1.6,1.7 armsim.h
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[Simit-arm-cvs] simit-arm/simulator biu.cpp,NONE,1.1 Makefile.am,1.4,1.5 armsim.cpp,1.6,1.7 armsim.hpp,1.4,1.5 cache.h,1.5,1.6 checker.cpp,1.1,1.2 main.cpp,1.5,1.6 BIU.h,1.3,NONE
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From: Wei Q. <wei...@us...> - 2005-08-21 04:23:20
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Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv6307 Modified Files: Makefile.am armsim.cpp armsim.hpp cache.h checker.cpp main.cpp Added Files: biu.cpp Removed Files: BIU.h Log Message: readies for smp Index: main.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/main.cpp,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** main.cpp 19 Aug 2005 03:15:05 -0000 1.5 --- main.cpp 21 Aug 2005 04:23:12 -0000 1.6 *************** *** 11,14 **** --- 11,15 ---- #endif + using emulator::memory; using namespace simulator; *************** *** 55,58 **** --- 56,79 ---- void (*prev_sig_handler)(int); + /* subsystem memory parameters */ + int n_mem_rlat = memoryReadLatency; // latency to load a cache block + int n_mem_wlat = memoryWriteLatency; // latency to write a cache block + int n_tlb_lat = tlbLoadLatency; // latency to serve a tlb miss + + int n_itlb_blk = nITLBBlocks; // # blocks in itlb + int n_itlb_assoc = nITLBAssoc; // # associativity of icache + int n_itlb_psize = IPageSize; // # bytes in a i-page + int n_dtlb_blk = nDTLBBlocks; // # blocks in dtlb + int n_dtlb_assoc = nDTLBAssoc; // # associativity of dcache + int n_dtlb_psize = DPageSize; // # bytes in a d-page + + int n_ic_blk = nICacheBlocks; // # blocks in icache + int n_ic_assoc = nICacheAssoc; // # associativity of icache + int n_ic_bsize = ICacheLineSize; // # bytes in a icache block + int n_dc_blk = nICacheBlocks; // # blocks in dcache + int n_dc_assoc = nICacheAssoc; // # associativity of dcache + int n_dc_bsize = ICacheLineSize; // # bytes in a dcache block + + for(i = 1; i < argc; i++) { *************** *** 66,70 **** prog_name = argv[i]; break; ! } } --- 87,91 ---- prog_name = argv[i]; break; ! } } *************** *** 72,76 **** if(prog_name) { ! sima = new arm_simulator(verbose, need_fpe, true); signal(SIGUSR1, sig_handler); --- 93,106 ---- if(prog_name) { ! memory *mem = new memory(); ! bus_interface *biu = ! new bus_interface("biu", mem, n_mem_rlat, n_mem_wlat); ! ! sima = new arm_simulator(verbose, need_fpe, true, ! n_ic_blk, n_ic_assoc, n_ic_bsize, ! n_dc_blk, n_dc_assoc, n_dc_bsize, ! n_itlb_blk, n_itlb_assoc, n_itlb_psize, ! n_dtlb_blk, n_dtlb_assoc, n_dtlb_psize, n_tlb_lat, ! mem, biu); signal(SIGUSR1, sig_handler); *************** *** 113,116 **** --- 143,148 ---- delete sima; + delete biu; + delete mem; } else usage(argv[0]); Index: cache.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/cache.h,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** cache.h 19 Aug 2005 03:15:05 -0000 1.5 --- cache.h 21 Aug 2005 04:23:12 -0000 1.6 *************** *** 5,9 **** #include <string> #include "misc.h" ! #include "BIU.h" namespace simulator { --- 5,9 ---- #include <string> #include "misc.h" ! #include "biu.h" namespace simulator { *************** *** 102,112 **** } - /* invalidate a line of cache */ - bool invalidate(target_addr_t addr) { - struct block_t *blk = look_up(addr); - if (!blk || !blk->valid) return false; - blk->valid = false; - return true; - } /* data access interfaces */ --- 102,105 ---- *************** *** 114,117 **** --- 107,115 ---- virtual bool write(target_addr_t addr, unsigned size, uint32_t *val) = 0; + /* to be called by biu for flushing, return the block of data */ + virtual uint8_t *biu_flush(target_addr_t addr) = 0; + virtual bool biu_invalidate(target_addr_t addr) = 0; + virtual bool is_block_dirty(target_addr_t addr) = 0; + virtual void update_on_clock() = 0; *************** *** 189,192 **** --- 187,206 ---- } + /* invalidate a line of cache */ + bool biu_invalidate(target_addr_t addr) { + tag_t *blk = look_up(addr); + if (!blk || !blk->valid) return false; + blk->valid = false; + return true; + } + + uint8_t *biu_flush(target_addr_t addr) { + return NULL; + } + + bool is_block_dirty(target_addr_t addr) { + return false; + } + void update_on_clock() { if (delay) delay--; *************** *** 274,278 **** reqTag = allocate_block(addr); reqTag->tag = get_tag(addr); - reqTag->valid = true; reqLine = values + (reqTag - tags); --- 288,291 ---- *************** *** 285,289 **** } else { ! biu->post_request(true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } --- 298,303 ---- } else { ! biu->post_request(this, true, ! aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } *************** *** 324,336 **** } void update_on_clock() { if (state==PENDING_LOAD) { if (!biu->is_busy()) { ! biu->post_request(true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } } ! else if (state==WAITING_LOAD && biu->get_ack()) { state = IDLE; } --- 338,368 ---- } + uint8_t *biu_flush(target_addr_t addr) { + return NULL; + } + + /* invalidate a line of cache */ + bool biu_invalidate(target_addr_t addr) { + tag_t *blk = look_up(addr); + if (!blk || !blk->valid) return false; + blk->valid = false; + return true; + } + + bool is_block_dirty(target_addr_t addr) { + return false; + } + void update_on_clock() { if (state==PENDING_LOAD) { if (!biu->is_busy()) { ! biu->post_request(this, true, ! aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } } ! else if (state==WAITING_LOAD && biu->get_ack(this)) { ! reqTag->valid = true; state = IDLE; } *************** *** 409,413 **** state = IDLE; - flush_only = false; nReads = 0; --- 441,444 ---- *************** *** 446,450 **** target_addr_t flush_index = (reqTag-tags)/n_assoc; flush_addr = get_address(flush_index, reqTag->tag); - flush_only = false; // if the channel is busy, wait */ --- 477,480 ---- *************** *** 453,457 **** } else { ! biu->post_request(false, flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } --- 483,488 ---- } else { ! biu->post_request(this, false, ! flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } *************** *** 464,468 **** } else { ! biu->post_request(true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } --- 495,500 ---- } else { ! biu->post_request(this, true, ! aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } *************** *** 470,474 **** reqTag->tag = get_tag(addr); - reqTag->valid = true; return false; --- 502,505 ---- *************** *** 544,547 **** --- 575,583 ---- nWrites++; + + /* notify the write so that others can invalidate their stale data + in a SMP configuration */ + biu->notify_write(this, addr); + return true; } *************** *** 563,567 **** target_addr_t flush_index = (reqTag-tags)/n_assoc; flush_addr = get_address(flush_index, reqTag->tag); - flush_only = false; // wait for biu --- 599,602 ---- *************** *** 570,574 **** } else { ! biu->post_request(false, flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } --- 605,610 ---- } else { ! biu->post_request(this, ! false, flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } *************** *** 580,584 **** } else { ! biu->post_request(true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } --- 616,621 ---- } else { ! biu->post_request(this, ! true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } *************** *** 586,590 **** reqTag->tag = get_tag(addr); - reqTag->valid = true; return false; --- 623,626 ---- *************** *** 593,623 **** /* flush the block containing addr, but does NOT invalidate */ ! bool flush_request(target_addr_t addr) { ! ! /* if cache busy, cannot do anything */ ! if (state!=IDLE) return false; ! /* if in cache, then update the cache line with data */ ! reqTag = look_up(addr); ! if (reqTag) { ! flush_addr = addr >> bsize_bits << bsize_bits; ! reqLine = values + (reqTag - tags); ! flush_only = true; ! if (reqLine->dirty) { ! // wait for biu ! if (biu->is_busy()) { ! state = PENDING_FLUSH; ! } ! else { ! biu->post_request(false, flush_addr, bsize, reqLine->data); ! state = WAITING_FLUSH; ! } } - return false; } ! else // nothing to be done ! return true; } --- 629,672 ---- /* flush the block containing addr, but does NOT invalidate */ ! uint8_t *biu_flush(target_addr_t addr) { ! tag_t *tag = look_up(addr); ! if (tag) { ! struct data_t *line = values + (tag - tags); ! // if pending to flush this line, can skip waiting ! if (state==PENDING_FLUSH && reqLine==line) { ! state = PENDING_LOAD; ! } ! if (line->dirty) { ! line->dirty = false; ! return line->data; } } ! return NULL; ! } ! ! /* invalidate a line of cache */ ! bool biu_invalidate(target_addr_t addr) { ! ! tag_t *blk = look_up(addr); ! ! if (!blk || !blk->valid) return false; ! ! struct data_t *line = values + (blk - tags); ! // this state should not occur ! assert (!(state==PENDING_FLUSH && reqLine==line)); ! blk->valid = false; ! return true; ! } ! ! bool is_block_dirty(target_addr_t addr) { ! tag_t *tag = look_up(addr); ! if (tag) { ! struct data_t *line = values + (tag - tags); ! return line ->dirty; ! } ! return false; } *************** *** 628,632 **** case PENDING_FLUSH: if (!biu->is_busy()) { ! biu->post_request(false, flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } --- 677,682 ---- case PENDING_FLUSH: if (!biu->is_busy()) { ! biu->post_request(this, ! false, flush_addr, bsize, reqLine->data); state = WAITING_FLUSH; } *************** *** 634,645 **** case WAITING_FLUSH: ! if (biu->get_ack()) { reqLine->dirty = false; ! if (flush_only) { ! state = IDLE; ! break; ! } ! else ! state = PENDING_LOAD; } // fall through here --- 684,690 ---- case WAITING_FLUSH: ! if (biu->get_ack(this)) { reqLine->dirty = false; ! state = PENDING_LOAD; } // fall through here *************** *** 647,651 **** case PENDING_LOAD: if (!biu->is_busy()) { ! biu->post_request(true, aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } --- 692,697 ---- case PENDING_LOAD: if (!biu->is_busy()) { ! biu->post_request(this, true, ! aligned_addr, bsize, reqLine->data); state = WAITING_LOAD; } *************** *** 653,657 **** case WAITING_LOAD: ! if (biu->get_ack()) state = IDLE; break; --- 699,706 ---- case WAITING_LOAD: ! if (biu->get_ack(this)) { ! state = IDLE; ! reqTag->valid = true; ! } break; *************** *** 692,697 **** uint64_t nWrites, nWriteMisses; - bool flush_only; - tag_t *reqTag; struct data_t *reqLine; --- 741,744 ---- Index: armsim.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.cpp,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** armsim.cpp 19 Aug 2005 03:15:05 -0000 1.6 --- armsim.cpp 21 Aug 2005 04:23:12 -0000 1.7 *************** *** 25,42 **** using std::list; ! arm_simulator::arm_simulator(bool verbose, bool need_fpe, bool emu_syscall) : ! verbose(verbose), need_fpe(need_fpe), emu_syscall(emu_syscall) { ! mem = new memory(); /* create the hardware modules */ ! biu = new BIU("biu", mem, memoryReadLatency, memoryWriteLatency); ! icache = new ICache("icache", nICacheBlocks, nICacheAssoc, ICacheLineSize, ! biu); ! dcache = new DCache("dcache", nDCacheBlocks, nDCacheAssoc, DCacheLineSize, ! biu); ! itlb = new ITLB("itlb", nITLBBlocks, nITLBAssoc, IPageSize, tlbLoadLatency); ! dtlb = new DTLB("dtlb", nDTLBBlocks, nDTLBAssoc, DPageSize, tlbLoadLatency); imcu = new mcu("imcu", itlb, icache); --- 25,56 ---- using std::list; ! arm_simulator::arm_simulator(bool verbose, bool need_fpe, bool emu_syscall, ! int n_ic_blk, int n_ic_assoc, int n_ic_bsize, ! int n_dc_blk, int n_dc_assoc, int n_dc_bsize, ! int n_itlb_blk, int n_itlb_assoc, int n_itlb_psize, ! int n_dtlb_blk, int n_dtlb_assoc, int n_dtlb_psize, int n_tlb_lat, ! memory *mem_, bus_interface *biu_) : ! verbose(verbose), need_fpe(need_fpe), emu_syscall(emu_syscall), ! mem(mem_), biu(biu_) { ! //mem = new memory(); ! use_self_mem = false; ! if (mem==NULL || biu==NULL) { ! mem = new memory(); ! biu = new bus_interface("biu", mem, ! memoryReadLatency, memoryWriteLatency); ! use_self_mem = true; ! } /* create the hardware modules */ ! //biu = new BIU("biu", mem, memoryReadLatency, memoryWriteLatency); ! icache = new ICache("icache", n_ic_blk, n_ic_assoc, n_ic_bsize, biu); ! dcache = new DCache("dcache", n_dc_blk, n_dc_assoc, n_dc_bsize, biu); ! itlb = new ITLB("itlb", n_itlb_blk, n_itlb_assoc, n_itlb_psize, n_tlb_lat); ! dtlb = new DTLB("dtlb", n_dtlb_blk, n_dtlb_assoc, n_dtlb_psize, n_tlb_lat); ! ! biu->register_icache(icache); ! biu->register_dcache(dcache); imcu = new mcu("imcu", itlb, icache); *************** *** 85,94 **** delete dev_master; ! delete biu; delete icache; delete itlb; delete dcache; delete dtlb; - delete mem; delete imcu; --- 99,111 ---- delete dev_master; ! if (use_self_mem) { ! delete biu; ! delete mem; ! } ! delete icache; delete itlb; delete dcache; delete dtlb; delete imcu; Index: Makefile.am =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/Makefile.am,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** Makefile.am 19 Aug 2005 03:15:05 -0000 1.4 --- Makefile.am 21 Aug 2005 04:23:12 -0000 1.5 *************** *** 21,30 **** libarmsim_a_SOURCES = define.cpp machines.cpp \ main.cpp armsim.cpp more_managers.cpp \ ! ext_func.cpp fetch_oper_dec.cpp \ mang_list.hpp armsim.hpp \ define.hpp include_osm.hpp \ include_temp.hpp more_managers.hpp interface.hpp \ cache.h fetch_oper_dec.hpp mach_list.hpp \ ! BIU.h machines.hpp parms.h mcu.h \ fetch_oper_pat.hpp fetch_oper_tab.hpp func.hpp \ $(top_builddir)/emulator/syscall.cpp \ --- 21,30 ---- libarmsim_a_SOURCES = define.cpp machines.cpp \ main.cpp armsim.cpp more_managers.cpp \ ! ext_func.cpp fetch_oper_dec.cpp biu.cpp \ mang_list.hpp armsim.hpp \ define.hpp include_osm.hpp \ include_temp.hpp more_managers.hpp interface.hpp \ cache.h fetch_oper_dec.hpp mach_list.hpp \ ! biu.h machines.hpp parms.h mcu.h \ fetch_oper_pat.hpp fetch_oper_tab.hpp func.hpp \ $(top_builddir)/emulator/syscall.cpp \ *************** *** 38,44 **** $(top_builddir)/emulator/external_dev_stub.o ! AM_CPPFLAGS = -DCOMPILE_SIMULATOR include_HEADERS = parms.h more_managers.hpp \ ! include_osm.hpp cache.h BIU.h armsim.hpp \ mach_list.hpp mang_list.hpp --- 38,44 ---- $(top_builddir)/emulator/external_dev_stub.o ! libarmsim_a_CPPFLAGS = -DCOMPILE_SIMULATOR include_HEADERS = parms.h more_managers.hpp \ ! include_osm.hpp cache.h biu.h armsim.hpp \ mach_list.hpp mang_list.hpp Index: armsim.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.hpp,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** armsim.hpp 19 Aug 2005 03:15:05 -0000 1.4 --- armsim.hpp 21 Aug 2005 04:23:12 -0000 1.5 *************** *** 20,25 **** namespace simulator { - typedef class bus_interface BIU; - /* forward declaration */ class device_emulator; --- 20,23 ---- *************** *** 50,54 **** * @param verbose Verbose mode */ ! arm_simulator(bool verbose, bool need_fpe, bool emulate_syscall); /** Destructor. */ --- 48,61 ---- * @param verbose Verbose mode */ ! arm_simulator(bool verbose, bool need_fpe, bool emulate_syscall, ! int n_ic_blk=nICacheBlocks, int n_ic_assoc=nICacheAssoc, ! int n_ic_bsize=ICacheLineSize, ! int n_dc_blk=nDCacheBlocks, int n_dc_assoc=nDCacheAssoc, ! int n_dc_bsize=DCacheLineSize, ! int n_itlb_blk=nITLBBlocks, int n_itlb_assoc=nITLBAssoc, ! int n_itlb_psize=IPageSize, ! int n_dtlb_blk=nDTLBBlocks, int n_dtlb_assoc=nDTLBAssoc, ! int n_dtlb_psize=DPageSize, int n_tlb_lat=tlbLoadLatency, ! emulator::memory *mem=NULL, bus_interface *biu=NULL); /** Destructor. */ *************** *** 161,164 **** --- 168,172 ---- /* memory saving the real data value */ emulator::memory *mem; + bus_interface *biu; /* the token managers */ *************** *** 235,238 **** --- 243,247 ---- bool emu_syscall; + bool use_self_mem; int retcode; // valid on ST_EXIT *************** *** 275,279 **** ITLB *itlb; DTLB *dtlb; - BIU *biu; mcu *imcu; mcu *dmcu; --- 284,287 ---- Index: checker.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/checker.cpp,v retrieving revision 1.1 retrieving revision 1.2 diff -C2 -d -r1.1 -r1.2 *** checker.cpp 19 Aug 2005 03:15:05 -0000 1.1 --- checker.cpp 21 Aug 2005 04:23:12 -0000 1.2 *************** *** 164,167 **** --- 164,168 ---- delete sima; + delete ema; } else usage(argv[0]); --- NEW FILE: biu.cpp --- #include "emumem.h" #include "cache.h" #include "biu.h" using std::vector; using namespace emulator; using namespace simulator; void bus_interface::smp_service_read(cache *cash, target_addr_t addr, unsigned size, void *ptr) { vector<cache *>::iterator cit; for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) { if ((*cit)->is_block_dirty(addr)) { uint8_t *pval = (*cit)->biu_flush(addr); if (pval) { // flush occurs // assuming sizes to be the same !!! mem->write_block(addr, pval, size); delay += write_latency; break; } } } mem->read_block(ptr, addr, size); } void bus_interface::smp_service_write(cache *cash, target_addr_t addr) { // need to invalidate all caches containing the address vector<cache *>::iterator cit; for (cit=dcaches.begin(); cit!=dcaches.end(); cit++) { (*cit)->biu_invalidate(addr); } } --- BIU.h DELETED --- |
