[Simit-arm-cvs] simit-arm/simulator/src arm.mad,1.2,1.3 syscall.mad,1.2,1.3

[Wei Q. <wei...@us...>]

Update of /cvsroot/simit-arm/simit-arm/simulator/src
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv10309/src

Modified Files:
	arm.mad syscall.mad 
Log Message:

Reorganizes cache, no longer uses template but uses C++ abstraction:
a base cache class and derived classes. Cache now holds real data.
Changes the syscall interpreter to account for this. Changes
memory read/write handling by introducing mcu.



Index: syscall.mad
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/src/syscall.mad,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** syscall.mad	25 Dec 2004 18:38:55 -0000	1.2
--- syscall.mad	19 Aug 2005 03:15:07 -0000	1.3
***************
*** 24,44 ****
  
  	TRANS 
! 	e_id_ex:	{ex_buffer = mEX[], v_iflag = *mCPSR[], !id_buffer};
  				 eval_pred(pred, cond, v_iflag);
  
  	e_ex_bf:	{pred>0, bf_buffer = mBF[]};
  
! 	e_bf_wb:	{wb_buffer = mWB[]};
! 				 sys_call(imm); # execute syscall till pipeline empty
  
! 	e_wb_in:	{!wb_buffer, !bf_buffer, !ex_buffer};
  
! 	e_ex_bf_null:	{pred==0, bf_buffer = mBF[], !!ex_buffer};
  	e_bf_wb_null:	{wb_buffer = mWB[], !!bf_buffer};
  	e_wb_in_null:	{!!wb_buffer};
  
!     e_ex_in:	{*mReset[], !!ex_buffer};
  
  
  OPERATION fpe
  
--- 24,44 ----
  
  	TRANS 
! 	e_id_ex:	{ex_buffer = mEX[], v_iflag = *mCPSR[]};
  				 eval_pred(pred, cond, v_iflag);
  
  	e_ex_bf:	{pred>0, bf_buffer = mBF[]};
  
! 	e_bf_wb:	{wb_buffer = mWB[], sc_buffer = mSC[imm]}; 
  
! 	e_wb_in:	{!sc_buffer, !wb_buffer, !bf_buffer, !ex_buffer, !id_buffer};
  
! 	e_ex_bf_null:	{pred==0, bf_buffer = mBF[], !!ex_buffer, !!id_buffer};
  	e_bf_wb_null:	{wb_buffer = mWB[], !!bf_buffer};
  	e_wb_in_null:	{!!wb_buffer};
  
!     e_ex_in:	{*mReset[], !!ex_buffer, !!id_buffer};
  
  
+ ##
  OPERATION fpe
  
***************
*** 69,74 ****
--- 69,158 ----
  
      e_ex_in:	{*mReset[], !!ex_buffer};
+ ##
+ 
+ OPERATION coproc_inst
+ 
+ 	VAR cp_oper : {cdp, mcr, mrc, ldc, stc};
+ 
+ 	SYNTAX cp_oper;
+ 	CODING cp_oper;
+ 
+ 	EVAL +cp_oper;
+ 
+ 	TRANS
+ 	e_id_ex:	{ex_buffer = mEX[], v_iflag = *mCPSR[]};
+ 				 eval_pred(pred, cond, v_iflag);
+ 
+ 	e_ex_bf:	{pred>0, bf_buffer = mBF[]};
+ 
+ 	e_bf_wb:	{wb_buffer = mWB[], cp_buffer = mCoProc[iw]};
+ 
+ 	e_wb_in:	{!cp_buffer, !wb_buffer, !bf_buffer, !ex_buffer, !id_buffer};
+ 
+ 	e_ex_bf_null:	{pred==0, bf_buffer = mBF[], !!ex_buffer, !!id_buffer};
+ 	e_bf_wb_null:	{wb_buffer = mWB[], !!bf_buffer};
+ 	e_wb_in_null:	{!!wb_buffer};
+ 
+     e_ex_in:	{*mReset[], !!ex_buffer, !!id_buffer};
+ 
+ 
+ OPERATION cdp
+ 
+ 	VAR cp_num:uint<4>;
+ 		opcd1:uint<4>;
+ 		opcd2:uint<3>;
+ 
+ 	SYNTAX "cdp"^cond_names[cond] "p"^cp_num ^"," opcd1 ^","
+ 			"cr"^rd ^"," "cr"^rn ^"," "cr"^rm ^"," opcd2;
+ 
+ 	CODING cond 1110 opcd1 rn rd cp_num opcd2 0 rm;
+ 
+ 
+ OPERATION mcr
+ 
+ 	VAR cp_num:uint<4>;
+ 		opcd1:uint<3>;
+ 		opcd2:uint<3>;
+ 
+ 	SYNTAX "mcr"^cond_names[cond] "p"^cp_num ^"," opcd1 ^","
+ 			reg_names[rd] ^"," "cr"^rn ^"," "cr"^rm ^"," opcd2;
+ 
+ 	CODING cond 1110 opcd1 0 rn rd cp_num opcd2 1 rm;
+ 
+ 
+ OPERATION mrc
+ 
+ 	VAR cp_num:uint<4>;
+ 		opcd1:uint<3>;
+ 		opcd2:uint<3>;
+ 
+ 	SYNTAX "mrc"^cond_names[cond] "p"^cp_num ^"," opcd1 ^","
+ 			reg_names[rd] ^"," "cr"^rn ^"," "cr"^rm ^"," opcd2;
+ 
+ 	CODING cond 1110 opcd1 1 rn rd cp_num opcd2 1 rm;
  
  
+ OPERATION ldc
+ 
+ 	VAR cp_num:uint<4>;
+ 		offset:uint<8>;
+ 
+ 	SYNTAX "ldc"^cond_names[cond] "p"^cp_num ^"," "cr"^rd ^", ...";
+ 
+ 	CODING cond 110----1 rn rd cp_num offset;
+ 
+ 
+ OPERATION stc
+ 
+ 	VAR cp_num:uint<4>;
+ 		offset:uint<8>;
+ 
+ 	SYNTAX "stc"^cond_names[cond] "p"^cp_num ^"," "cr"^rd ^", ...";
+ 
+ 	CODING cond 110----0 rn rd cp_num offset;
+ 
+ 
+ 
+ ##
  OPERATION coproc_ld
  
***************
*** 117,119 ****
  
      e_ex_in:	{*mReset[], !!ex_buffer};
! 
--- 201,203 ----
  
      e_ex_in:	{*mReset[], !!ex_buffer};
! ##

Index: arm.mad
===================================================================
RCS file: /cvsroot/simit-arm/simit-arm/simulator/src/arm.mad,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** arm.mad	25 Dec 2004 18:38:55 -0000	1.2
--- arm.mad	19 Aug 2005 03:15:07 -0000	1.3
***************
*** 84,88 ****
  		# reset manager, written by all operation writing to gpr
  		reset_manager : void -> (uint<4>, uint<1>);
! 		coproc_manager : (uint<1>, uint<1>) -> void;
  
  	INSTANCE
--- 84,89 ----
  		# reset manager, written by all operation writing to gpr
  		reset_manager : void -> (uint<4>, uint<1>);
! 		coproc_manager : uint<32> -> void;
! 		syscall_manager: uint<24> -> void;
  
  	INSTANCE
***************
*** 109,112 ****
--- 110,114 ----
  
  		mCoProc : coproc_manager;
+ 		mSC		: syscall_manager;
  
  
***************
*** 179,182 ****
--- 181,185 ----
  
  		   cp_buffer : coproc_manager;
+ 		   sc_buffer : syscall_manager;
  
  	# states for lds/stm operations
***************
*** 261,266 ****
  			  store_imm, store_reg, store_ext_imm, store_ext_reg,
  			  swap, ldm, stm,
! 			  mult, mult_long, syscall, fpe,
! 			  coproc_ld, coproc_st}(unknown); # unknown as the default
  
  		rec:{fetch};
--- 264,269 ----
  			  store_imm, store_reg, store_ext_imm, store_ext_reg,
  			  swap, ldm, stm,
! 			  mult, mult_long, syscall, 
! 			  coproc_inst}(unknown); # unknown as the default
  
  		rec:{fetch};