[Simit-arm-cvs] simit-arm/simulator checker.cpp,NONE,1.1 mcu.hpp,NONE,1.1 BIU.h,1.2,1.3 Makefile.am,
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[Simit-arm-cvs] simit-arm/simulator checker.cpp,NONE,1.1 mcu.hpp,NONE,1.1 BIU.h,1.2,1.3 Makefile.am,1.3,1.4 armsim.cpp,1.5,1.6 armsim.hpp,1.3,1.4 cache.h,1.4,1.5 fetch_oper_pat.hpp,1.4,1.5 fetch_oper_tab.hpp,1.2,1.3 machines.cpp,1.5,1.6 machines.hpp,1.2,1.3 main.cpp,1.4,1.5 mang_list.hpp,1.2,1.3 more_managers.cpp,1.2,1.3 more_managers.hpp,1.3,1.4
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From: Wei Q. <wei...@us...> - 2005-08-19 03:15:16
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Update of /cvsroot/simit-arm/simit-arm/simulator In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv10309 Modified Files: BIU.h Makefile.am armsim.cpp armsim.hpp cache.h fetch_oper_pat.hpp fetch_oper_tab.hpp machines.cpp machines.hpp main.cpp mang_list.hpp more_managers.cpp more_managers.hpp Added Files: checker.cpp mcu.hpp Log Message: Reorganizes cache, no longer uses template but uses C++ abstraction: a base cache class and derived classes. Cache now holds real data. Changes the syscall interpreter to account for this. Changes memory read/write handling by introducing mcu. Index: machines.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/machines.hpp,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** machines.hpp 12 Nov 2004 06:33:02 -0000 1.2 --- machines.hpp 19 Aug 2005 03:15:05 -0000 1.3 *************** *** 1243,1254 **** L_$S_EX$38081, /*1229*/ L_$S_BF$38083, /*1230*/ ! L_$S_ID$38150, /*1231*/ ! L_$S_EX$38151, /*1232*/ ! L_$S_BF$38153, /*1233*/ ! L_$S_ID$38220, /*1234*/ ! L_$S_EX$38221, /*1235*/ ! L_$S_ID$38290, /*1236*/ ! L_$S_EX$38291, /*1237*/ ! L_$S_BF$38293, /*1238*/ }; --- 1243,1254 ---- L_$S_EX$38081, /*1229*/ L_$S_BF$38083, /*1230*/ ! L_$S_WB$38100, /*1231*/ ! L_$S_ID$38150, /*1232*/ ! L_$S_ID$38220, /*1233*/ ! L_$S_ID$38290, /*1234*/ ! L_$S_ID$38360, /*1235*/ ! L_$S_ID$38430, /*1236*/ ! L_$S_EX$38431, /*1237*/ ! L_$S_BF$38433, /*1238*/ }; *************** *** 1890,1901 **** bool L_$e_id_ex$38105(); bool L_$e_bf_wb$38128(); ! bool L_$e_id_ex$38175(); ! bool L_$e_ex_bf$38179(); ! bool L_$e_bf_wb$38198(); ! bool L_$e_id_ex$38245(); ! bool L_$e_ex_bf$38249(); ! bool L_$e_id_ex$38315(); ! bool L_$e_ex_bf$38319(); ! bool L_$e_bf_wb$38338(); --- 1890,1897 ---- bool L_$e_id_ex$38105(); bool L_$e_bf_wb$38128(); ! bool L_$e_wb_in$38146(); ! bool L_$e_id_ex$38455(); ! bool L_$e_ex_bf$38459(); ! bool L_$e_bf_wb$38478(); *************** *** 1944,1947 **** --- 1940,1944 ---- _UINT_T(10) C_34; _UINT_T(64) C_35; + _UINT_T(3) C_36; _UINT_T(32) _temp_coding; *************** *** 1996,1999 **** --- 1993,1997 ---- _MANG_CLASS(regfile_manager)::TOKEN_T *B_dst15; _MANG_CLASS(coproc_manager)::TOKEN_T *B_cp_buffer; + _MANG_CLASS(syscall_manager)::TOKEN_T *B_sc_buffer; #endif void __dec_0(); *************** *** 2545,2548 **** --- 2543,2548 ---- void __dec_546(); void __dec_547(); + void __dec_548(); + void __dec_549(); }; Index: more_managers.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/more_managers.hpp,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** more_managers.hpp 12 Nov 2004 06:40:32 -0000 1.3 --- more_managers.hpp 19 Aug 2005 03:15:05 -0000 1.4 *************** *** 21,31 **** namespace simulator { /* forward declaration*/ ! typedef class rcache<nICacheBlocks, nICacheAssoc, ! ICacheLineSize, memoryReadLatency> ICache; ! typedef class rwcache<nDCacheBlocks, nDCacheAssoc, ! DCacheLineSize, memoryReadLatency, memoryWriteLatency> DCache; ! typedef class rcache<nITLBBlocks, nITLBAssoc, IPageSize, tlbLoadLatency> ITLB; ! typedef class rcache<nDTLBBlocks, nDTLBAssoc, DPageSize, tlbLoadLatency> DTLB; /** The register file. */ --- 21,31 ---- namespace simulator { + class mcu; + /* forward declaration*/ ! typedef class rcache ICache; ! typedef class rwcache DCache; ! typedef class tlb ITLB; ! typedef class tlb DTLB; /** The register file. */ *************** *** 298,302 **** fetch_manager(const std::string& name) : name(name), token(new TOKEN_T(this)), ! fetch_status(0), trigger(false) {} /** Destructor. */ --- 298,302 ---- fetch_manager(const std::string& name) : name(name), token(new TOKEN_T(this)), ! status(0), trigger(false) {} /** Destructor. */ *************** *** 324,328 **** */ bool token_good_to_reclaim(TOKEN_T *token, _BASE_MACHINE *obj) { ! return fetch_status==0; } --- 324,328 ---- */ bool token_good_to_reclaim(TOKEN_T *token, _BASE_MACHINE *obj) { ! return status==0; } *************** *** 332,336 **** TOKEN_T *allocate_token(_BASE_MACHINE *obj) { token->set_used(obj); ! fetch_status = 1; trigger = true; return token; --- 332,336 ---- TOKEN_T *allocate_token(_BASE_MACHINE *obj) { token->set_used(obj); ! status = 1; trigger = true; return token; *************** *** 365,373 **** _UINT_T(32) read_token(_BASE_MACHINE *obj, TOKEN_T *token) { - unsigned iw = mem->read_word_fast(current_pc); - #ifdef DEBUG - //fprintf(stderr, "0x%08x\n", current_pc); - fprintf(stderr, "0x%08x : 0x%08x\n", current_pc, iw); - #endif return iw; } --- 365,368 ---- *************** *** 375,389 **** /** Connect the fetcher with other modules. * @param mrf The register file manager, for program counter. ! * @param csh The instruction cache object. ! * @param tlb The instruction tlb object. ! * @param imm The memory to get instrution from. */ ! void connect(regfile_manager *mrf, reset_manager *mrs, ! ICache *csh, ITLB *tlb, emulator::memory *imm) { mRF = mrf; mRS = mrs; ! icache = csh; ! itlb = tlb; ! mem = imm; } --- 370,380 ---- /** Connect the fetcher with other modules. * @param mrf The register file manager, for program counter. ! * @param mrs The reset manager. ! * @param csh The instruction memory controller. */ ! void connect(regfile_manager *mrf, reset_manager *mrs, mcu *csh) { mRF = mrf; mRS = mrs; ! imcu = csh; } *************** *** 395,401 **** trigger = false; token->set_unused(); ! fetch_status = 0; } private: --- 386,397 ---- trigger = false; token->set_unused(); ! status = 0; ! branch_taken = false; ! first_inst = true; } + /** get the current pc */ + unsigned get_current_pc(); + private: *************** *** 404,416 **** unsigned current_pc; /* the pc currently fetching */ ! int fetch_status; /* state of fetching. */ int trigger; /* start a new request. */ /* connected components. */ regfile_manager *mRF; reset_manager *mRS; ! ICache *icache; ! ITLB *itlb; ! emulator::memory *mem; }; --- 400,415 ---- unsigned current_pc; /* the pc currently fetching */ ! int status; /* state of fetching. */ int trigger; /* start a new request. */ + word_t iw; /* connected components. */ regfile_manager *mRF; reset_manager *mRS; ! mcu *imcu; ! ! // two flags for debugging ! int branch_taken, first_inst; ! }; *************** *** 432,436 **** */ mem_ctrl_port(const std::string& name) : ! name(name), count(0), status(0), mergeable(false), trigger(false) {} /** Destructor. */ --- 431,435 ---- */ mem_ctrl_port(const std::string& name) : ! name(name), count(0), status(0), trigger(false) {} /** Destructor. */ *************** *** 473,492 **** /** Connect the module with other modules. ! * @param csh The data cache object. ! * @param tlb The data tlb object. * @param rpt The memory read port. * @param wpt The memory write port. - * @param dmm The data memory containing real data. * @param map The memory address port. * @param reg The register file. */ ! void connect(DCache *csh, DTLB *tlb, ! mem_read_port *rpt, mem_write_port *wpt, emulator::memory *dmm, mem_addr_port *map, regfile_manager *reg) { ! dcache = csh; ! dtlb = tlb; mMemRead = rpt; mMemWrite = wpt; - mem = dmm; mMemAddr = map; mRF = reg; --- 472,487 ---- /** Connect the module with other modules. ! * @param csh The data memory controller. * @param rpt The memory read port. * @param wpt The memory write port. * @param map The memory address port. * @param reg The register file. */ ! void connect(mcu *csh, ! mem_read_port *rpt, mem_write_port *wpt, mem_addr_port *map, regfile_manager *reg) { ! dmcu = csh; mMemRead = rpt; mMemWrite = wpt; mMemAddr = map; mRF = reg; *************** *** 499,502 **** --- 494,498 ---- void reset() { status = 0; + count = 0; } *************** *** 509,523 **** unsigned addr; unsigned size; - bool mergeable; bool isRead; bool trigger; ! DCache *dcache; ! DTLB *dtlb; mem_read_port *mMemRead; mem_write_port *mMemWrite; mem_addr_port *mMemAddr; regfile_manager *mRF; - emulator::memory *mem; }; --- 505,518 ---- unsigned addr; unsigned size; bool isRead; bool trigger; ! uint32_t val; ! ! mcu *dmcu; mem_read_port *mMemRead; mem_write_port *mMemWrite; mem_addr_port *mMemAddr; regfile_manager *mRF; }; *************** *** 711,742 **** }; ! class coproc_manager { public: /** index type. */ ! typedef _TUPLE_T(_UINT_T(1),_UINT_T(1)) I; /** token type. */ ! typedef class _token_<coproc_manager> TOKEN_T; /** Constructor. * @param name Name of the register file */ ! coproc_manager(const std::string& name) : name(name), state(0) { token = new TOKEN_T(this); } /** Destructor. */ ! ~coproc_manager() { delete token; } ! /** See if token is available for inquire. * @param ind The index of the token. * @param obj The OSM sending the request. */ bool token_free_for_alloc(const I& ind, _BASE_MACHINE *obj) { ! return token->is_free(); } --- 706,738 ---- }; ! class syscall_manager { public: /** index type. */ ! typedef _UINT_T(24) I; /** token type. */ ! typedef class _token_<syscall_manager> TOKEN_T; /** Constructor. * @param name Name of the register file */ ! syscall_manager(const std::string& name) : name(name) { token = new TOKEN_T(this); + reset(); } /** Destructor. */ ! ~syscall_manager() { delete token; } ! /** See if token is available for allocation. * @param ind The index of the token. * @param obj The OSM sending the request. */ bool token_free_for_alloc(const I& ind, _BASE_MACHINE *obj) { ! return true; } *************** *** 746,750 **** */ bool token_good_to_reclaim(TOKEN_T *token, _BASE_MACHINE *obj) { ! return state==0; } --- 742,746 ---- */ bool token_good_to_reclaim(TOKEN_T *token, _BASE_MACHINE *obj) { ! return !busy; } *************** *** 754,759 **** */ TOKEN_T *allocate_token(const I& ind, _BASE_MACHINE *obj) { ! state = ind.first.val()?2:1; ! has_addr = ind.second.val(); return token; } --- 750,755 ---- */ TOKEN_T *allocate_token(const I& ind, _BASE_MACHINE *obj) { ! sc_num = ind.val() & 0x3FF; ! trigger = busy = true; return token; } *************** *** 769,773 **** /** Discard a token. * @param token The token to discard. ! * @param obj The OSM sending the request. */ void discard_token(TOKEN_T *token, _BASE_MACHINE *obj) { --- 765,769 ---- /** Discard a token. * @param token The token to discard. ! * @param obj The OSM sending the request. */ void discard_token(TOKEN_T *token, _BASE_MACHINE *obj) { *************** *** 780,808 **** } ! /** Connect the fetcher with other modules. ! * @param mrf The register file manager, for program counter. ! * @param imm The memory to get instrution from. */ ! void connect(regfile_manager *mrf, emulator::memory *imm) { ! mRF = mrf; ! mem = imm; } ! /** Register the device master . */ ! void register_dev_master(emulator::device_master *dev) { ! dev_emul = dev; } ! /** Free those temporarily allocated. */ ! void update_on_clock() { ! if (state==0) return; ! else if (state==1) do_read(); ! else do_write(); } /** Resetting states. */ void reset() { - state = 0; token->set_unused(); } --- 776,888 ---- } ! void update_on_clock(); ! ! /** Resetting states. */ ! void reset() { ! token->set_unused(); ! trigger = in_fpe = busy = false; ! } ! ! void set_armsim(arm_simulator *armsim) { ! _armsim = armsim; ! } ! ! private: ! ! std::string name; ! ! TOKEN_T *token; ! unsigned sc_num; ! ! bool in_fpe; ! bool busy; ! bool trigger; ! ! // for access to cycle count ! arm_simulator *_armsim; ! }; ! ! class coproc_manager { ! ! public: ! ! /** index type. */ ! typedef _UINT_T(32) I; ! ! /** token type. */ ! typedef class _token_<coproc_manager> TOKEN_T; ! ! /** Constructor. ! * @param name Name of the register file */ ! coproc_manager(const std::string& name) : name(name) { ! token = new TOKEN_T(this); ! reset(); } ! /** Destructor. */ ! ~coproc_manager() { ! delete token; } ! /** See if token is available for allocation. ! * @param ind The index of the token. ! * @param obj The OSM sending the request. ! */ ! bool token_free_for_alloc(const I& ind, _BASE_MACHINE *obj) { ! return true; ! } ! ! /** See if it is ok to release token. ! * @param token The token to release. ! * @param obj The OSM sending the request. ! */ ! bool token_good_to_reclaim(TOKEN_T *token, _BASE_MACHINE *obj) { ! return !busy; } + /** Allocate a token. + * @param ind The index of the token. + * @param obj The OSM sending the request. + */ + TOKEN_T *allocate_token(const I& ind, _BASE_MACHINE *obj) { + iw = ind.val(); + trigger = true; + #ifndef ENABLE_CP + fprintf(stderr, "Coprocessor instruction ignored 0x%08x!\n", iw); + #endif + return token; + } + + /** Release a token. + * @param token The token to release. + * @param obj The OSM sending the request. + */ + void reclaim_token(TOKEN_T *token, _BASE_MACHINE *obj) { + } + + /** Discard a token. + * @param token The token to discard. + * @param obj The OSM sending the request. + */ + void discard_token(TOKEN_T *token, _BASE_MACHINE *obj) { + } + + /** Get the name of the manager. */ + const std::string& get_name() { + return name; + } + + void trigger_coproc(); + void update_on_clock(); + /** Resetting states. */ void reset() { token->set_unused(); + trigger = busy = false; + } + + void set_armsim(arm_simulator *armsim) { + _armsim = armsim; } *************** *** 810,827 **** std::string name; - TOKEN_T *token; - - regfile_manager *mRF; - emulator::memory *mem; ! bool has_addr; // has address or not ! int state; // 0: nothing, 1 to read, 2 to write ! emulator::device_master *dev_emul; ! void do_read(); ! void do_write(); }; } --- 890,905 ---- std::string name; ! TOKEN_T *token; ! uint32_t iw; ! bool busy; ! bool trigger; ! // for access to cycle count ! arm_simulator *_armsim; }; + } Index: more_managers.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/more_managers.cpp,v retrieving revision 1.2 retrieving revision 1.3 diff -C2 -d -r1.2 -r1.3 *** more_managers.cpp 12 Nov 2004 06:33:02 -0000 1.2 --- more_managers.cpp 19 Aug 2005 03:15:05 -0000 1.3 *************** *** 1,4 **** --- 1,5 ---- #include "more_managers.hpp" + #include "mcu.hpp" #include "armsim.hpp" #include "emu_device.hpp" *************** *** 6,12 **** --- 7,44 ---- using namespace simulator; + + unsigned fetch_manager::get_current_pc() + { + #ifdef ARMSIM_SERIALIZE + if (branch_taken | first_inst) + return mRF->get_pc().val(); + else + return mRF->get_pc().val()-4; + #else + return mRF->get_pc().val(); + #endif + } + void fetch_manager::update_on_clock() { + /* for debugging use, disables pipelining */ + #ifdef ARMSIM_SERIALIZE + if (mRS->branch_taken()) + branch_taken = 1; + #endif + /* a new OSM comes in */ + #ifdef ARMSIM_SERIALIZE + if (trigger) { + if (branch_taken | first_inst) + current_pc = mRF->get_pc().val(); + else + current_pc = mRF->get_pc().val()-4; + branch_taken = 0; + mRF->set_pc(current_pc+8); + trigger = false; + first_inst = 0; + } + #else if (trigger) { current_pc = mRF->get_pc().val(); *************** *** 14,27 **** trigger = false; } ! if (fetch_status==1) { ! if (itlb->read(current_pc, 4)) { ! fetch_status = 2; ! } } ! if (fetch_status==2) { ! if (icache->read(current_pc, 4)) { ! fetch_status = 0; ! } } } --- 46,61 ---- trigger = false; } + #endif ! if (status==1 && !imcu->is_busy()) { ! imcu->start_read(current_pc, &iw, 4); ! status = 2; } ! if (status==2 && !imcu->is_busy()) { ! status = 0; ! #ifdef DEBUG ! //fprintf(stderr, "0x%08x\n", current_pc); ! fprintf(stderr, "0x%08x : 0x%08x\n", current_pc, iw); ! #endif } } *************** *** 30,39 **** { if (trigger) { - assert(status==0); status = 1; - addr = mMemAddr->get_value().val(); - mergeable = count > 0; trigger = false; } else if (count>0) { --- 64,71 ---- { if (trigger) { assert(status==0); status = 1; trigger = false; + addr = mMemAddr->get_value().val(); } else if (count>0) { *************** *** 45,128 **** } ! if (status==1) { ! if (dtlb->read(addr, size)) ! status = 2; } ! if (status==2) { ! if (isRead && dcache->read(addr, size)) { ! if (size==4) { ! mMemRead->set_value(mem->read_word(addr)); ! } ! else if (size==1) { ! mMemRead->set_value(mem->read_byte(addr)); ! } ! else { ! mMemRead->set_value(mem->read_half_word(addr)); ! } ! status = 0; ! #if 0 ! std::cerr << "read once " << std::hex << addr << " " ! << mMemRead->get_value() << " " ; #endif ! } ! if (!isRead && dcache->write(addr, size, mergeable)) { ! if (size==4) { ! mem->write_word(addr, mMemWrite->get_value().val()); ! } ! else if (size==1) { ! mem->write_byte(addr, mMemWrite->get_value().val()); ! } ! else { ! mem->write_half_word(addr, mMemWrite->get_value().val()); ! } ! status = 0; #if 0 ! std::cerr << "write once " << std::hex << addr << " " ! << mMemWrite->get_value() << " " ; #endif - } - } } ! void coproc_manager::do_read() { ! // r0 contains the device id ! dev_id_t id = mRF->get_value(0).val(); ! // r1 contains the address ! dev_addr_t addr = mRF->get_value(1).val(); ! dev_data_t data; ! if (has_addr) { ! if (dev_emul->receive(id, data, addr)) { ! state = 0; ! mRF->set_value(0, data); ! } ! } ! else if (dev_emul->receive(id, data)) { ! state = 0; ! mRF->set_value(0, data); ! } } ! void coproc_manager::do_write() { ! // r0 contains the device id ! dev_id_t id = mRF->get_value(0).val(); ! // r2 contains the address ! dev_addr_t addr = mRF->get_value(2).val(); ! // r1 contains the value to write ! dev_data_t data = mRF->get_value(1).val(); ! if (has_addr) { ! if (dev_emul->send(id, data, addr)) ! state = 0; } ! else if (dev_emul->send(id, data)) { ! state = 0; } } --- 77,228 ---- } ! // step 1, waiting for MMU to be available ! if (status==1 && !dmcu->is_busy()) { ! ! if (isRead) ! dmcu->start_read(addr, &val, size); ! else { ! val = mMemWrite->get_value().val(); ! dmcu->start_write(addr, &val, size); ! } ! ! status = 2; } ! // step 2, waiting for MMU to finish ! if (status==2 && !dmcu->is_busy()) { ! if (isRead) mMemRead->set_value(val); ! status = 0; ! #ifdef DEBUG ! if (size==1) val = val&0xFF; ! else if (size==2) val = val&0xFFFF; ! fprintf(stderr, "mem %d %x %x\n", isRead, addr, val); #endif ! } ! } ! ! void syscall_manager::update_on_clock() ! { ! if (trigger) { ! trigger = false; ! _armsim->syscall_start(sc_num); ! busy = true; ! } ! else if (busy) { ! busy = _armsim->syscall_busy(); ! } ! } ! ! #if 0 ! ! void sfu2x2_manager::read_value(unsigned index, uint32_t &val1, uint32_t &val2) ! { ! #ifdef ENABLE_SFU ! _armsim->sfu2x2_read(index, val1, val2); ! //fprintf(stderr, "read value %d %d %d\n", index, val1, val2); #endif } ! void sfu2x2_manager::write_value(unsigned index, uint32_t val1, uint32_t val2) { ! #ifdef ENABLE_SFU ! _armsim->sfu2x2_write(index, val1, val2); ! //fprintf(stderr, "write value %d %d %d\n", index, val1, val2); ! #endif ! } ! void sfu3x1_manager::read_value(unsigned index, uint32_t &val) ! { ! #ifdef ENABLE_SFU ! _armsim->sfu3x1_read(index, val); ! //fprintf(stderr, "read value %d %d\n", index, val); ! #endif ! } ! void sfu3x1_manager::write_value(unsigned index, uint32_t val1, ! uint32_t val2, uint32_t val3) ! { ! #ifdef ENABLE_SFU ! _armsim->sfu3x1_write(index, val1, val2, val3); ! //fprintf(stderr, "write value %d %d %d\n", index, val1, val2); ! #endif ! } ! void sfu2x1_manager::read_value(unsigned index, uint32_t &val) ! { ! #ifdef ENABLE_SFU ! _armsim->sfu2x1_read(index, val); ! //fprintf(stderr, "read value %d %d\n", index, val); ! #endif } ! void sfu2x1_manager::write_value(unsigned index, uint32_t val1, uint32_t val2) { ! #ifdef ENABLE_SFU ! _armsim->sfu2x1_write(index, val1, val2); ! //fprintf(stderr, "write value %d %d %d\n", index, val1, val2); ! #endif ! } ! #endif ! void coproc_manager::update_on_clock() ! { ! #ifdef ENABLE_CP ! if (trigger) { ! trigger = false; ! busy = true; ! _armsim->coproc_start(iw); } ! else if (busy) { ! busy = _armsim->coproc_busy(); ! ! if (!busy) { ! arm_simulator::CP_FLAG flag = _armsim->coproc_status(); ! switch (flag) { ! case arm_simulator::CP_FLAG_NORMAL: ! //good, do nothing ! break; ! case arm_simulator::CP_FLAG_ILLEGAL: ! fprintf(stderr, "Illegal " ! "coprocessor instruction 0x%08x\n", iw); ! break; ! case arm_simulator::CP_FLAG_NO_ACK: ! fprintf(stderr, "Error processing coprocessor " ! "instruction 0x%08x : " ! "no coprocessor responds\n", iw); ! break; ! case arm_simulator::CP_FLAG_WRITE_PC: ! fprintf(stderr, "Illegal coprocessor " ! "instruction 0x%08x : " ! "writing to PC\n", iw); ! break; ! case arm_simulator::CP_FLAG_ERROR: ! fprintf(stderr, "Error processing " ! "coprocessor instruction 0x%08x\n", iw); ! break; ! case arm_simulator::CP_FLAG_OVERFLOW: ! fprintf(stderr, "Abnormal coprocessor behavior " ! "for instruction 0x%08x : " ! " more than 16 memory references.\n", iw); ! raise(SIGINT); ! break; ! case arm_simulator::CP_FLAG_EARLY_DONE: ! fprintf(stderr, "Abnormal coprocessor behavior " ! "for instruction 0x%08x : " ! "done signal earlier than expected.\n", iw); ! raise(SIGINT); ! break; ! case arm_simulator::CP_FLAG_TIME_OUT: ! fprintf(stderr, "Abnormal coprocessor behavior " ! "for instruction 0x%08x : " ! "time out.\n", iw); ! raise(SIGINT); ! break; ! } ! } } + #endif } Index: cache.h =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/cache.h,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** cache.h 21 May 2005 20:28:48 -0000 1.4 --- cache.h 19 Aug 2005 03:15:05 -0000 1.5 *************** *** 4,332 **** #include <string> #include "BIU.h" namespace simulator { ! struct cache_block { ! uint32_t tag; ! bool valid; ! bool dirty[2]; [...997 lines suppressed...] ! target_addr_t flush_addr; // flush addr ! ! enum { ! IDLE, ! PENDING_FLUSH, ! WAITING_FLUSH, ! PENDING_LOAD, ! WAITING_LOAD ! } state; ! ! uint64_t nReads, nReadMisses; ! uint64_t nWrites, nWriteMisses; ! ! bool flush_only; ! ! tag_t *reqTag; ! struct data_t *reqLine; ! struct data_t *values; //[n_block/n_assoc][n_assoc]; }; Index: armsim.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/armsim.cpp,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** armsim.cpp 20 May 2005 06:11:27 -0000 1.5 --- armsim.cpp 19 Aug 2005 03:15:05 -0000 1.6 *************** *** 2,5 **** --- 2,6 ---- #include "armsim.hpp" #include "more_managers.hpp" + #include "mcu.hpp" #include "machines.hpp" *************** *** 28,39 **** { /* create the hardware modules */ ! biu = new BIU("biu"); ! icache = new ICache("icache", *biu); ! itlb = new ITLB("itlb", *biu); ! dcache = new DCache("dcache", *biu); ! dtlb = new DTLB("dtlb", *biu); ! mem = new memory(); /* Create the managers */ --- 29,45 ---- { + mem = new memory(); + /* create the hardware modules */ ! biu = new BIU("biu", mem, memoryReadLatency, memoryWriteLatency); ! icache = new ICache("icache", nICacheBlocks, nICacheAssoc, ICacheLineSize, ! biu); ! dcache = new DCache("dcache", nDCacheBlocks, nDCacheAssoc, DCacheLineSize, ! biu); ! itlb = new ITLB("itlb", nITLBBlocks, nITLBAssoc, IPageSize, tlbLoadLatency); ! dtlb = new DTLB("dtlb", nDTLBBlocks, nDTLBAssoc, DPageSize, tlbLoadLatency); ! imcu = new mcu("imcu", itlb, icache); ! dmcu = new mcu("dmcu", dtlb, dcache); /* Create the managers */ *************** *** 42,52 **** /* conenct the managers. */ ! mIF->connect(mRF, mReset, icache, itlb, mem); ! mMemCtrl->connect(dcache, dtlb, mMemRead, mMemWrite, mem, mMemAddr, mRF); mNewPC->connect(mRF); ! mCoProc->connect(mRF, mem); dev_master = new device_master(); ! mCoProc->register_dev_master(dev_master); init_devices(dev_master); --- 48,61 ---- /* conenct the managers. */ ! mIF->connect(mRF, mReset, imcu); ! mMemCtrl->connect(dmcu, mMemRead, mMemWrite, mMemAddr, mRF); mNewPC->connect(mRF); ! mSC->set_armsim(this); ! mCoProc->set_armsim(this); ! ! //mCoProc->connect(mRF, mem); dev_master = new device_master(); ! //mCoProc->register_dev_master(dev_master); init_devices(dev_master); *************** *** 54,57 **** --- 63,68 ---- machine_pool = new obj_pool<_opt_machine_, _MACH_ID_T, arm_simulator, arm_simulator::mach_allocator>(_mach_total); + + syscall_buf = NULL; /* reset every thing */ *************** *** 61,64 **** --- 72,80 ---- arm_simulator::~arm_simulator() { + // flush the pipeline + for (work_it=work_list.begin(); work_it!=work_list.end();) { + sink_machine(*work_it); + work_it = work_list.erase(work_it); + } delete machine_pool; *************** *** 75,78 **** --- 91,100 ---- delete dtlb; delete mem; + + delete imcu; + delete dmcu; + + if (syscall_buf) free(syscall_buf); + } *************** *** 80,87 **** { mem->reset(); ! icache->reset(); ! dcache->reset(); ! itlb->reset(); ! dtlb->reset(); biu->reset(); --- 102,107 ---- { mem->reset(); ! imcu->reset(); ! dmcu->reset(); biu->reset(); *************** *** 101,104 **** --- 121,138 ---- status = ST_RESET; in_fpe = false; + + inst_done = false; + + syscall_phase = 0; + syscall_state = SYSCALL_IDLE; + if (syscall_buf) { + free(syscall_buf); + syscall_buf = NULL; + } + + for (work_it=work_list.begin(); work_it!=work_list.end();) { + sink_machine(*work_it); + work_it = work_list.erase(work_it); + } } *************** *** 112,120 **** void arm_simulator::dump_stats(FILE *fp) { ! icache->PrintStats(fp); ! itlb->PrintStats(fp); ! dcache->PrintStats(fp); ! dtlb->PrintStats(fp); ! biu->PrintStats(fp); fprintf(fp, "Total allocated OSMs : %lld\n", alloc_count); --- 146,154 ---- void arm_simulator::dump_stats(FILE *fp) { ! icache->print_stats(fp); ! itlb->print_stats(fp); ! dcache->print_stats(fp); ! dtlb->print_stats(fp); ! biu->print_stats(fp); fprintf(fp, "Total allocated OSMs : %lld\n", alloc_count); *************** *** 170,216 **** #undef DEBUG_CYCLE #ifdef DEBUG_CYCLE ! fprintf(stderr, "--clock %d--\n", cycle_count); #endif ! /** Activate all OSMs in order. */ ! for (work_it=work_list.begin(); work_it!=work_list.end();) { ! ins_it = work_it; ! ins_it++; #if defined DEBUG_CYCLE || defined DEBUG ! int oldstate = (*work_it)->__get_state(); #endif ! bool ret = (*work_it)->__activate(); #ifdef DEBUG_CYCLE ! std::cerr << (*work_it)->__get_dynid() << " " << oldstate << "->"; ! std::cerr << (*work_it)->__get_state() << " " << ret << std::endl; #endif ! /* Test if the OSM is back to the initial state. */ ! if (ret) { /* no */ ! work_it++; ! } ! else { /* yes */ - /* send retired ones to the sink. */ - sink_machine(*work_it); - work_it = work_list.erase(work_it); - } } ! cycle_count++; ! mMemCtrl->update_on_clock(); ! mNewPC->update_on_clock(); ! mIF->update_on_clock(); ! mReset->update_on_clock(); ! mEX->update_on_clock(); ! mCoProc->update_on_clock(); ! icache->updateOnClockTick(); ! itlb->updateOnClockTick(); ! dcache->updateOnClockTick(); ! dtlb->updateOnClockTick(); ! biu->updateOnClockTick(); } --- 204,263 ---- #undef DEBUG_CYCLE #ifdef DEBUG_CYCLE ! fprintf(stderr, "--clock %d--\n", cycle_count); #endif ! #ifdef ARMSIM_SERIALIZE ! inst_done = false; ! #endif ! /** Activate all OSMs in order. */ ! for (work_it=work_list.begin(); work_it!=work_list.end();) { ! ! ins_it = work_it; ! ins_it++; #if defined DEBUG_CYCLE || defined DEBUG ! int oldstate = (*work_it)->__get_state(); #endif ! bool ret = (*work_it)->__activate(); #ifdef DEBUG_CYCLE ! std::cerr << (*work_it)->__get_dynid() << " " << oldstate << "->"; ! std::cerr << (*work_it)->__get_state() << " " << ret << std::endl; #endif ! /* Test if the OSM is back to the initial state. */ ! if (ret) { /* no */ ! work_it++; ! } ! else { /* yes */ ! ! /* send retired ones to the sink. */ ! sink_machine(*work_it); ! work_it = work_list.erase(work_it); ! ! #ifdef ARMSIM_SERIALIZE ! inst_done = true; ! #endif } + #ifdef ARMSIM_SERIALIZE + break; + #endif + } ! cycle_count++; ! mMemCtrl->update_on_clock(); ! mNewPC->update_on_clock(); ! mIF->update_on_clock(); ! mReset->update_on_clock(); ! mEX->update_on_clock(); ! mCoProc->update_on_clock(); ! mSC->update_on_clock(); ! imcu->update_on_clock(); ! dmcu->update_on_clock(); ! biu->update_on_clock(); ! ! syscall_update(); } *************** *** 222,226 **** status = ST_RUNNING; ! while(status==ST_RUNNING && cycle_count<=maxCycle) { clock_tick(); } --- 269,273 ---- status = ST_RUNNING; ! while(status==ST_RUNNING && cycle_count<maxCycle) { clock_tick(); } *************** *** 268,269 **** --- 315,424 ---- } + + /* Syscall related functions begin */ + void arm_simulator::syscall_start(unsigned int num) + { + assert(syscall_state==SYSCALL_IDLE); + syscall_num = num; + sc_impl(this, syscall_num); + } + + void arm_simulator::syscall_update() + { + switch (syscall_state) { + + case SYSCALL_PENDING_MEM_READ: + + if (!dmcu->is_busy()) { + + syscall_state = SYSCALL_WAITING_MEM_READ; + + dmcu->start_read_block(syscall_mem_addr, + syscall_mem_ptr, syscall_mem_size); + } + break; + + case SYSCALL_WAITING_MEM_READ: + + if (!dmcu->is_busy()) { + syscall_state = SYSCALL_IDLE; + } + break; + + case SYSCALL_PENDING_MEM_WRITE: + + if (!dmcu->is_busy()) { + + syscall_state = SYSCALL_WAITING_MEM_READ; + + dmcu->start_write_block(syscall_mem_addr, + syscall_mem_ptr, syscall_mem_size); + } + break; + + case SYSCALL_WAITING_MEM_WRITE: + + if (!dmcu->is_busy()) { + syscall_state = SYSCALL_IDLE; + } + break; + + default: break; + + } + + // call syscall handler another time + if (syscall_state==SYSCALL_IDLE && syscall_phase) + sc_impl(this, syscall_num); + } + + void arm_simulator::syscall_mem_read_block(target_addr_t addr, + uint8_t *ptr, unsigned size) + { + assert(syscall_state == SYSCALL_IDLE); + assert(ptr!=NULL); + assert(size>0); + + syscall_state = SYSCALL_PENDING_MEM_READ; + syscall_mem_addr = addr; + syscall_mem_size = size; + syscall_mem_ptr = ptr; + } + + void arm_simulator::syscall_mem_write_block(target_addr_t addr, + uint8_t *ptr, unsigned size) + { + assert(syscall_state == SYSCALL_IDLE); + assert(ptr!=NULL); + assert(size>0); + + syscall_state = SYSCALL_PENDING_MEM_WRITE; + syscall_mem_addr = addr; + syscall_mem_size = size; + syscall_mem_ptr = ptr; + } + + void arm_simulator::syscall_realloc_buf(unsigned size) + { + assert(syscall_buf!=NULL); + syscall_buf = realloc(syscall_buf, size); + if (syscall_buf==NULL) { + fprintf(stderr, "Error: Out of host memory when allocating %d" + " bytes for a system call.\n", size); + exit(-1); + } + } + + void arm_simulator::syscall_alloc_buf(unsigned size) + { + if (syscall_buf!=NULL) + free(syscall_buf); + + syscall_buf = malloc(size); + if (syscall_buf==NULL) { + fprintf(stderr, "Error: Out of host memory when reallocating %d" + " bytes for a system call.\n", size); + exit(-1); + } + } + Index: Makefile.am =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/Makefile.am,v retrieving revision 1.3 retrieving revision 1.4 diff -C2 -d -r1.3 -r1.4 *** Makefile.am 20 May 2005 06:11:27 -0000 1.3 --- Makefile.am 19 Aug 2005 03:15:05 -0000 1.4 *************** *** 1,10 **** ! bin_PROGRAMS = sima sima_SOURCES = main.cpp sima_LDADD = libarmsim.a ! AM_CPPFLAGS = -D__COMPILE_SIMULATOR_ INCLUDES = -I$(top_srcdir)/libosm -I$(top_srcdir)/emulator -I$(top_builddir)/emulator --- 1,15 ---- ! bin_PROGRAMS = sima checker sima_SOURCES = main.cpp sima_LDADD = libarmsim.a ! checker_SOURCES = checker.cpp armsim.cpp more_managers.cpp ! checker_CPPFLAGS = -DARMSIM_SERIALIZE -DCOMPILE_SIMULATOR ! checker_LDADD = libarmsim.a $(top_builddir)/emulator/libarmemu.a ! checker_LDFLAGS = -z muldefs ! ! INCLUDES = -I$(top_srcdir)/libosm -I$(top_srcdir)/emulator -I$(top_builddir)/emulator *************** *** 21,25 **** include_temp.hpp more_managers.hpp interface.hpp \ cache.h fetch_oper_dec.hpp mach_list.hpp \ ! BIU.h machines.hpp parms.h \ fetch_oper_pat.hpp fetch_oper_tab.hpp func.hpp \ $(top_builddir)/emulator/syscall.cpp \ --- 26,30 ---- include_temp.hpp more_managers.hpp interface.hpp \ cache.h fetch_oper_dec.hpp mach_list.hpp \ ! BIU.h machines.hpp parms.h mcu.h \ fetch_oper_pat.hpp fetch_oper_tab.hpp func.hpp \ $(top_builddir)/emulator/syscall.cpp \ *************** *** 33,36 **** --- 38,43 ---- $(top_builddir)/emulator/external_dev_stub.o + AM_CPPFLAGS = -DCOMPILE_SIMULATOR + include_HEADERS = parms.h more_managers.hpp \ include_osm.hpp cache.h BIU.h armsim.hpp \ Index: fetch_oper_pat.hpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/fetch_oper_pat.hpp,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** fetch_oper_pat.hpp 2 Mar 2005 21:46:16 -0000 1.4 --- fetch_oper_pat.hpp 19 Aug 2005 03:15:05 -0000 1.5 *************** *** 3,10 **** Input statistics ! Total entries : 1289 ! Unique labels : 548 ! Shannon entropy : 9.09208 ! Huffman tree height : 9.12751 Decoder characteristics --- 3,10 ---- Input statistics ! Total entries : 1284 ! Unique labels : 550 ! Shannon entropy : 9.10075 ! Huffman tree height : 9.13662 Decoder characteristics *************** *** 82,101 **** _STUB_DEC(stub_0_126) _STUB_DEC(stub_0_127) ! _STUB_DEC(stub_0_208) ! _STUB_DEC(stub_0_209) ! _STUB_DEC(stub_0_210) ! _STUB_DEC(stub_0_211) ! _STUB_DEC(stub_0_212) ! _STUB_DEC(stub_0_213) ! _STUB_DEC(stub_0_214) ! _STUB_DEC(stub_0_215) ! _STUB_DEC(stub_0_216) ! _STUB_DEC(stub_0_217) ! _STUB_DEC(stub_0_218) ! _STUB_DEC(stub_0_219) ! _STUB_DEC(stub_0_220) ! _STUB_DEC(stub_0_221) ! _STUB_DEC(stub_0_222) ! _STUB_DEC(stub_0_223) _STUB_DEC(stub_1_0) _STUB_DEC(stub_1_2) --- 82,101 ---- _STUB_DEC(stub_0_126) _STUB_DEC(stub_0_127) ! _STUB_DEC(stub_0_224) ! _STUB_DEC(stub_0_225) ! _STUB_DEC(stub_0_226) ! _STUB_DEC(stub_0_227) ! _STUB_DEC(stub_0_228) ! _STUB_DEC(stub_0_229) ! _STUB_DEC(stub_0_230) ! _STUB_DEC(stub_0_231) ! _STUB_DEC(stub_0_232) ! _STUB_DEC(stub_0_233) ! _STUB_DEC(stub_0_234) ! _STUB_DEC(stub_0_235) ! _STUB_DEC(stub_0_236) ! _STUB_DEC(stub_0_237) ! _STUB_DEC(stub_0_238) ! _STUB_DEC(stub_0_239) _STUB_DEC(stub_1_0) _STUB_DEC(stub_1_2) *************** *** 340,356 **** /* ! Table begin: index=0 size=1289 Mask=0x0ff00ff0 DMask=0x00000000 CMask=0x08000000 Sig=0x03000000 ! Prob=549.005 Entropy=9.09208418 HTreeHeight=9.1275125 ------------------------------------------------------------------- mask=0x0f000000 sig=0x0a000000 prob=0.00182147704 name=DEC_fetch_oper_branch_ mask=0x0f000000 sig=0x0b000000 prob=0.00182147704 name=DEC_fetch_oper_branch_link_ ! mask=0x0f000200 sig=0x0d000000 prob=0.000455369259 name=DEC_fetch_oper_fpe_ ! mask=0x0f000400 sig=0x0d000200 prob=0.000455369259 name=DEC_fetch_oper_fpe_ ! mask=0x0f000800 sig=0x0d000600 prob=0.000455369259 name=DEC_fetch_oper_fpe_ ! mask=0x0f100200 sig=0x0d100c00 prob=0.000151789753 name=DEC_fetch_oper_fpe_ ! mask=0x0f100400 sig=0x0d100a00 prob=0.000151789753 name=DEC_fetch_oper_fpe_ ! mask=0x0f100800 sig=0x0d100600 prob=0.000151789753 name=DEC_fetch_oper_fpe_ ! mask=0x0f100e00 sig=0x0d000e00 prob=0.00182147704 name=DEC_fetch_oper_coproc_st_ mask=0x0ff00000 sig=0x02a00000 prob=0.00182147704 name=DEC_fetch_oper_dpi_imm_binop_adc_ mask=0x0ff00000 sig=0x02b00000 prob=0.00182147704 name=DEC_fetch_oper_dpi_imm_binop_adcs_ --- 340,354 ---- /* ! Table begin: index=0 size=1284 Mask=0x0ff00ff0 DMask=0x00000000 CMask=0x08000000 Sig=0x03000000 ! Prob=549.005 Entropy=9.10074509 HTreeHeight=9.13661989 ------------------------------------------------------------------- mask=0x0f000000 sig=0x0a000000 prob=0.00182147704 name=DEC_fetch_oper_branch_ mask=0x0f000000 sig=0x0b000000 prob=0.00182147704 name=DEC_fetch_oper_branch_link_ ! mask=0x0f000010 sig=0x0e000000 prob=0.00182147704 name=DEC_fetch_oper_coproc_inst_cdp_ ! mask=0x0e100000 sig=0x0c100000 prob=0.00182147704 name=DEC_fetch_oper_coproc_inst_ldc_ ! mask=0x0f100010 sig=0x0e000010 prob=0.00182147704 name=DEC_fetch_oper_coproc_inst_mcr_ ! mask=0x0f100010 sig=0x0e100010 prob=0.00182147704 name=DEC_fetch_oper_coproc_inst_mrc_ ! mask=0x0e100000 sig=0x0c000000 prob=0.00182147704 name=DEC_fetch_oper_coproc_inst_stc_ mask=0x0ff00000 sig=0x02a00000 prob=0.00182147704 name=DEC_fetch_oper_dpi_imm_binop_adc_ mask=0x0ff00000 sig=0x02b00000 prob=0.00182147704 name=DEC_fetch_oper_dpi_imm_binop_adcs_ *************** *** 1165,1171 **** mask=0x0ff000f0 sig=0x01e00070 prob=0.00182147704 name=DEC_fetch_oper_dpi_rshift_unop_r_ror_mvn_ mask=0x0ff000f0 sig=0x01f00070 prob=0.00182147704 name=DEC_fetch_oper_dpi_rshift_unop_r_ror_mvns_ - mask=0x0f000000 sig=0x0c000000 prob=0.00182147704 name=DEC_fetch_oper_fpe_ - mask=0x0f000000 sig=0x0e000000 prob=0.00182147704 name=DEC_fetch_oper_fpe_ - mask=0x0f100e00 sig=0x0d100e00 prob=0.00182147704 name=DEC_fetch_oper_coproc_ld_ mask=0x0e300000 sig=0x08100000 prob=0.00182147704 name=DEC_fetch_oper_ldm_noupdate_rn_ mask=0x0e300000 sig=0x08300000 prob=0.00182147704 name=DEC_fetch_oper_ldm_update_rn_ --- 1163,1166 ---- *************** *** 1829,1880 **** _FUNC_NAME(DEC_fetch_oper_branch_link_), _FUNC_NAME(DEC_fetch_oper_branch_link_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _STUB_NAME(stub_0_208), ! _STUB_NAME(stub_0_209), ! _STUB_NAME(stub_0_210), ! _STUB_NAME(stub_0_211), ! _STUB_NAME(stub_0_212), ! _STUB_NAME(stub_0_213), ! _STUB_NAME(stub_0_214), ! _STUB_NAME(stub_0_215), ! _STUB_NAME(stub_0_216), ! _STUB_NAME(stub_0_217), ! _STUB_NAME(stub_0_218), ! _STUB_NAME(stub_0_219), ! _STUB_NAME(stub_0_220), ! _STUB_NAME(stub_0_221), ! _STUB_NAME(stub_0_222), ! _STUB_NAME(stub_0_223), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), ! _FUNC_NAME(DEC_fetch_oper_fpe_), _FUNC_NAME(DEC_fetch_oper_syscall_), _FUNC_NAME(DEC_fetch_oper_syscall_), --- 1824,1875 ---- _FUNC_NAME(DEC_fetch_oper_branch_link_), _FUNC_NAME(DEC_fetch_oper_branch_link_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_stc_), ! _FUNC_NAME(DEC_fetch_oper_coproc_inst_ldc_), ! _STUB_NAME(stub_0_224), ! _STUB_NAME(stub_0_225), ! _STUB_NAME(stub_0_226), ! _STUB_NAME(stub_0_227), ! _STUB_NAME(stub_0_228), ! _STUB_NAME(stub_0_229), ! _STUB_NAME(stub_0_230), ! _STUB_NAME(stub_0_231), ! _STUB_NAME(stub_0_232), ! _STUB_NAME(stub_0_233), ! _STUB_NAME(stub_0_234), ! _STUB_NAME(stub_0_235), ! _STUB_NAME(stub_0_236), ! _STUB_NAME(stub_0_237), ! _STUB_NAME(stub_0_238), ! _STUB_NAME(stub_0_239), _FUNC_NAME(DEC_fetch_oper_syscall_), _FUNC_NAME(DEC_fetch_oper_syscall_), *************** *** 5522,5666 **** } ! _STUB_ENTRY(stub_0_208) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_209) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_210) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_211) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_212) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_213) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_214) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_215) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_216) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_217) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_218) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_219) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_220) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_221) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_222) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_st_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } ! _STUB_ENTRY(stub_0_223) { ! if _PATTERN_TRUE(0x00000e00, 0x00000e00) { ! _FUNC_CALL(DEC_fetch_oper_coproc_ld_); } else { ! _FUNC_CALL(DEC_fetch_oper_fpe_); } } --- 5517,5661 ---- } ! _STUB_ENTRY(stub_0_224) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_225) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_226) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_227) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_228) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_229) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_230) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_231) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_232) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_233) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_234) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_235) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_236) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_237) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } ! _STUB_ENTRY(stub_0_238) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mcr_); } } ! _STUB_ENTRY(stub_0_239) { ! if _PATTERN_TRUE(0x00000010, 0x00000000) { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_cdp_); } else { ! _FUNC_CALL(DEC_fetch_oper_coproc_inst_mrc_); } } Index: main.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/main.cpp,v retrieving revision 1.4 retrieving revision 1.5 diff -C2 -d -r1.4 -r1.5 *** main.cpp 20 May 2005 06:11:27 -0000 1.4 --- main.cpp 19 Aug 2005 03:15:05 -0000 1.5 *************** *** 59,63 **** if(strcmp(argv[i], "-v") == 0) verbose = true; else if(strcmp(argv[i], "-f") == 0) fpe_name = argv[++i]; else ! if(strcmp(argv[i], "-nf") == 0) need_fpe = false; if(strcmp(argv[i], "-m") == 0) max_cnum = ato_uint64(argv[++i]); else if(strcmp(argv[i], "-h") == 0) {usage(argv[0]); return 0;} else --- 59,63 ---- if(strcmp(argv[i], "-v") == 0) verbose = true; else if(strcmp(argv[i], "-f") == 0) fpe_name = argv[++i]; else ! if(strcmp(argv[i], "-nf") == 0) need_fpe = false; else if(strcmp(argv[i], "-m") == 0) max_cnum = ato_uint64(argv[++i]); else if(strcmp(argv[i], "-h") == 0) {usage(argv[0]); return 0;} else Index: machines.cpp =================================================================== RCS file: /cvsroot/simit-arm/simit-arm/simulator/machines.cpp,v retrieving revision 1.5 retrieving revision 1.6 diff -C2 -d -r1.5 -r1.6 *** machines.cpp 2 Feb 2005 17:53:34 -0000 1.5 --- machines.cpp 19 Aug 2005 03:15:05 -0000 1.6 *************** *** 118,128 **** #define V_syscall_coding C_3 #define V_syscall_imm C_28 ! #define V_fpe_syn C_14 ! #define V_fpe_coding C_5 ! #define V_fpe_pc C_3 ! #define V_coproc_ld_coding C_3 ! #define V_coproc_ld_has_addr C_10 ! #define V_coproc_st_coding C_3 ! #define V_coproc_st_has_addr C_10 #define V_and_coding C_29 #define V_eor_coding C_29 --- 118,122 ---- #define V_syscall_coding C_3 #define V_syscall_imm C_28 ! #define V_coproc_inst_coding C_3 #define V_and_coding C_29 #define V_eor_coding C_29 *************** *** 233,236 **** --- 227,248 ---- #define V_umlals_coding C_12 #define V_umlals_result C_35 + #define V_cdp_coding C_5 + #define V_cdp_cp_num C_1 + #define V_cdp_opcd1 C_9 + #define V_cdp_opcd2 C_12 + #define V_mcr_coding C_5 + #define V_mcr_cp_num C_1 + #define V_mcr_opcd1 C_12 + #define V_mcr_opcd2 C_36 + #define V_mrc_coding C_5 + #define V_mrc_cp_num C_1 + #define V_mrc_opcd1 C_12 + #define V_mrc_opcd2 C_36 + #define V_ldc_coding C_5 + #define V_ldc_offset C_2 + #define V_ldc_cp_num C_1 + #define V_stc_coding C_5 + #define V_stc_offset C_2 + #define V_stc_cp_num C_1 _MACH_CLASS(fetch_normal)::_MACH_CLASS(fetch_normal)(_SIMULATOR *sim):_BASE_MACHINE(sim, 1) { *************** *** 261,264 **** --- 273,277 ---- B_dst15 = NULL; B_cp_buffer = NULL; + B_sc_buffer = NULL; #endif *************** *** 9208,9232 **** } void _MACH_CLASS(fetch_normal)::__dec_544() { ! V_fpe_coding = _temp_coding; ! _MVR(G_cond) = _UINT_XTR2(V_fpe_coding, 31, 28); ! _DIRTY_E_FUN_REF(fpe_syntax, V_fpe_syn, V_fpe_coding); _state_ = L_$S_ID$38080; } void _MACH_CLASS(fetch_normal)::__dec_545() { ! V_coproc_ld_coding = _temp_coding; ! _MVR(G_cond) = _UINT_XTR2(V_coproc_ld_coding, 31, 28); ! V_coproc_ld_has_addr = _UINT_XTR1(V_coproc_ld_coding, 8); _state_ = L_$S_ID$38150; } void _MACH_CLASS(fetch_normal)::__dec_546() { ! V_coproc_st_coding = _temp_coding; ! _MVR(G_cond) = _UINT_XTR2(V_coproc_st_coding, 31, 28); ! V_coproc_st_has_addr = _UINT_XTR1(V_coproc_st_coding, 8); _state_ = L_$S_ID$38220; } void _MACH_CLASS(fetch_normal)::__dec_547() { _state_ = L_$S_ID$38290; } typedef void (_MACH_CLASS(fetch_normal)::*__DECODE_FTYPE)(); static const __DECODE_FTYPE __decs[] = { --- 9221,9287 ---- } void _MACH_CLASS(fetch_normal)::__dec_544() { ! V_coproc_inst_coding = _temp_coding; ! V_cdp_coding = _UINT_XTR2(V_coproc_inst_coding, 31, 0); ! _MVR(G_cond) = _UINT_XTR2(V_cdp_coding, 31, 28); ! V_cdp_opcd1 = _UINT_XTR2(V_cdp_coding, 23, 20); ! _MVR(G_rn) = _UINT_XTR2(V_cdp_coding, 19, 16); ! _MVR(G_rd) = _UINT_XTR2(V_cdp_coding, 15, 12); ! V_cdp_cp_num = _UINT_XTR2(V_cdp_coding, 11, 8); ! V_cdp_opcd2 = _UINT_XTR2(V_cdp_coding, 7, 5); ! _MVR(G_rm) = _UINT_XTR2(V_cdp_coding, 3, 0); _state_ = L_$S_ID$38080; } void _MACH_CLASS(fetch_normal)::__dec_545() { ! V_coproc_inst_coding = _temp_coding; ! V_mcr_coding = _UINT_XTR2(V_coproc_inst_coding, 31, 0); ! _MVR(G_cond) = _UINT_XTR2(V_mcr_coding, 31, 28); ! V_mcr_opcd1 = _UINT_XTR2(V_mcr_coding, 23, 21); ! _MVR(G_rn) = _UINT_XTR2(V_mcr_coding, 19, 16); ! _MVR(G_rd) = _UINT_XTR2(V_mcr_coding, 15, 12); ! V_mcr_cp_num = _UINT_XTR2(V_mcr_coding, 11, 8); ! V_mcr_opcd2 = _UINT_XTR2(V_mcr_coding, 7, 5); ! _MVR(G_rm) = _UINT_XTR2(V_mcr_coding, 3, 0); ! _state_ = L_$S_ID$38150; } void _MACH_CLASS(fetch_normal)::__dec_546() { ! V_coproc_inst_coding = _temp_coding; ! V_mrc_coding = _UINT_XTR2(V_coproc_inst_coding, 31, 0); ! _MVR(G_cond) = _UINT_XTR2(V_mrc_coding, 31, 28); ! V_mrc_opcd1 = _UINT_XTR2(V_mrc_coding, 23, 21); ! _MVR(G_rn) = _UINT_XTR2(V_mrc_coding, 19, 16); ! _MVR(G_rd) = _UINT_XTR2(V_mrc_coding, 15, 12); ! V_mrc_cp_num = _UINT_XTR2(V_mrc_coding, 11, 8); ! V_mrc_opcd2 = _UINT_XTR2(V_mrc_coding, 7, 5); ! _MVR(G_rm) = _UINT_XTR2(V_mrc_coding, 3, 0); ! _state_ = L_$S_ID$38220; } void _MACH_CLASS(fetch_normal)::__dec_547() { + V_coproc_inst_coding = _temp_coding; + V_ldc_coding = _UINT_XTR2(V_coproc_inst_coding, 31, 0); + _MVR(G_cond) = _UINT_XTR2(V_ldc_coding, 31, 28); + _MVR(G_rn) = _UINT_XTR2(V_ldc_coding, 19, 16); + _MVR(G_rd) = _UINT_XTR2(V_ldc_coding, 15, 12); + V_ldc_cp_num = _UINT_XTR2(V_ldc_coding, 11, 8); + V_ldc_offset = _UINT_XTR2(V_ldc_coding, 7, 0); + _state_ = L_$S_ID$38290; } + void _MACH_CLASS(fetch_normal)::__dec_548() { + V_coproc_inst_coding = _temp_coding; + V_stc_coding = _UINT_XTR2(V_coproc_inst_coding, 31, 0); + _MVR(G_cond) = _UINT_XTR2(V_stc_coding, 31, 28); + _MVR(G_rn) = _UINT_XTR2(V_stc_coding, 19, 16); + _MVR(G_rd) = _UINT_XTR2(V_stc_coding, 15, 12); + V_stc_cp_num = _UINT_XTR2(V_stc_coding, 11, 8); + V_stc_offset = _UINT_XTR2(V_stc_coding, 7, 0); + + _state_ = L_$S_ID$38360; + } + void _MACH_CLASS(fetch_normal)::__dec_549() { + _state_ = L_$S_ID$38430; + } typedef void (_MACH_CLASS(fetch_normal)::*__DECODE_FTYPE)(); static const __DECODE_FTYPE __decs[] = { *************** *** 9779,9782 **** --- 9834,9839 ---- &_MACH_CLASS(fetch_normal)::__dec_546, &_MACH_CLASS(fetch_normal)::__dec_547, + &_MACH_CLASS(fetch_normal)::__dec_548, + &_MACH_CLASS(fetch_normal)::__dec_549, }; *************** *** 29344,29348 **** if (!_TEST_ALLOCATE(mEX)) return false; if (!_TEST_INQUIRE(mCPSR)) return false; - if (!_TEST_RELEASE(B_id_buffer)) return false; _BUF(B_ex_buffer) = _ALLOCATE(mEX); --- 29401,29404 ---- *************** *** 29356,29361 **** _FUN_REF(F_eval_pred, _MVR(G_pred), _MVR(G_cond), _MVR(G_v_iflag)); - _RELEASE(B_id_buffer); - return true; } --- 29412,29415 ---- *************** *** 29370,29377 **** bool _MACH_CLASS(fetch_normal)::L_$e_bf_wb$38058() { if (!_TEST_ALLOCATE(mWB)) return false; ! _BUF(B_wb_buffer) = _ALLOCATE(mWB); ! _DIRTY_E_FUN_REF(sys_call, _U2U(24,32,V_syscall_imm)); return true; --- 29424,29432 ---- bool _MACH_CLASS(fetch_normal)::L_$e_bf_wb$38058() { + if (!_TEST_ALLOCATE_ID(mSC, V_syscall_imm)) return false; if (!_TEST_ALLOCATE(mWB)) return false; ! _BUF(B_sc_buffer) = _ALLOCATE_ID(mSC, V_syscall_imm); ! _BUF(B_wb_buffer) = _ALLOCATE(mWB); return true; *************** *** 29379,29385 **** --- 29434,29444 ---- bool _MACH_CLASS(fetch_normal)::L_$e_wb_in$38076() { + if (!_TEST_RELEASE(B_id_buffer)) return false; if (!_TEST_RELEASE(B_ex_buffer)) return false; if (!_TEST_RELEASE(B_bf_buffer)) return false; if (!_TEST_RELEASE(B_wb_buffer)) return false; + if (!_TEST_RELEASE(B_sc_buffer)) return false; + _RELEASE(B_id_buffer); + _RELEASE(B_ex_buffer); *************** *** 29388,29391 **** --- 29447,29452 ---- _RELEASE(B_wb_buffer); + _RELEASE(B_sc_buffer); + return true; } *************** *** 29393,29409 **** bool _MACH_CLASS(fetch_normal)::L_$e_id_ex$38105() { if (!_TEST_ALLOCATE(mEX)) return false; - if (!_TEST_INQUIRE_ID(mRF, _UINT_CTR(4, 0xf))) return false; if (!_TEST_INQUIRE(mCPSR)) return false; - if (!_TEST_RELEASE(B_id_buffer)) return false; _BUF(B_ex_buffer) = _ALLOCATE(mEX); { - _UINT_T(32) L_temp; - _READ_TOKEN_ID(L_temp,mRF, _UINT_CTR(4, 0xf)); - V_fpe_pc = L_temp; - } - - - { _UINT_T(4) L_temp; _READ_TOKEN(L_temp,mCPSR); --- 29454,29461 ---- *************** *** 29414,29474 **** _FUN_REF(F_eval_pred, _MVR(G_pred), _MVR(G_cond), _MVR(G_v_iflag)); - _RELEASE(B_id_buffer); - return true; } bool _MACH_CLASS(fetch_normal)::L_$e_bf_wb$38128() { if (!_TEST_ALLOCATE(mWB)) return false; ! if (!(_TEST_ALLOCATE(mReset))) return false; ! _BUF(B_wb_buffer) = _ALLOCATE(mWB); ! ! _DIRTY_E_FUN_REF(fpe_emul, _MVR(G_iw), V_fpe_pc); ! ! { ! _WRITE_TOKEN(mReset, _TUPLE_CTR(_UINT_T(4), _UINT_T(1), _UINT_CTR(4, 0xf), _UINT_CTR(1, 0x1))); ! } return true; } ! bool _MACH_CLASS(fetch_normal)::L_$e_id_ex$38175() { ! if (!_TEST_ALLOCATE(mEX)) return false; ! if (!_TEST_INQUIRE(mCPSR)) return false; if (!_TEST_RELEASE(B_id_buffer)) return false; - _BUF(B_ex_buffer) = _ALLOCATE(mEX); - - { - _UINT_T(4) L_temp; - _READ_TOKEN(L_temp,mCPSR); - _MVR(G_v_iflag) = L_temp; - } - - - _FUN_REF(F_eval_pred, _MVR(G_pred), _MVR(G_cond), _MVR(G_v_iflag)); - - _RELEASE(B_id_buffer); - - return true; - } - - bool _MACH_CLASS(fetch_normal)::L_$e_ex_bf$38179() { - if (!_COMPARE(_MVR(G_pred), >, _UINT_CTR(1, 0x0))) return false; - if (!_TEST_ALLOCATE_ID(mCoProc, _TUPLE_CTR(_UINT_T(1), _UINT_T(1), _UINT_CTR(1, 0x0), V_coproc_ld_has_addr))) return false; - if (!_TEST_ALLOCATE(mBF)) return false; - _BUF(B_cp_buffer) = _ALLOCATE_ID(mCoProc, _TUPLE_CTR(_UINT_T(1), _UINT_T(1), _UINT_CTR(1, 0x0), V_coproc_ld_has_addr)); - - _BUF(B_bf_buffer) = _ALLOCATE(mBF); - - return true; - } - - bool _MACH_CLASS(fetch_normal)::L_$e_bf_wb$38198() { - if (!_TEST_ALLOCATE(mWB)) return false; i... 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