On 21/03/12 10:10, nussgipfel@... wrote:
> Am Mi, 21.03.2012, 08:37, schrieb Bert Vermeulen:
>> The general idea of an FPGA doing sampling into fast RAM,
>> compression into slower RAM (but lots of it), and a separate USB
>> interface chip taking care of interfacing to a USB host is solid,
>> in my opinion.
> Yes, general this is solid. Depending on the Interface chip you get
> also network or USB3 nowadays.
Indeed. So in the interest of aiming high -- where else are you going to
aim -- let me throw some ideas onto the list.
- A three-stage capture with a series of chunks of fast RAM being used
for temporary real-time sample storage, combined with longer-term
compressed sample storage to a larger+slower RAM chip. Transfer to the
host happens from there, freeing the slower RAM when a chunk reaches the
host. This is a streaming design, very important -- sigrok does
*everything* streaming, and it has many advantages.
- I see no particular advantage in using USB, when ethernet connectivity
is cheap and readily available in many devices. With ethernet you get to
take advantage of the fact that just about everything you plug it into
can build up a queue, at any of several layers, and you have built-in
retransmission out of queues when something gets dropped. This is one of
the problems in a streaming design, after all, as we see on FX2-based
devices. Like I said, aim high: there's no point in making a new design
using old limitations.
- Something that came out of a brainstorming session with Peter Stuge:
it shouldn't be all that hard to have triggering that's more than your
basic multi-stage 1-0-1 or whatever. Having a built-in facility to keep
state of SPI and I2C captures would let you trigger on those. They're
both very simple protocols on the wire, seems quite doable on an FPGA.
This will go a LONG way for a lot of use cases -- so many devices use those.
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