On 2013-06-23 01:51, Ignacio García Pérez wrote:

Hi all,
(fl2lafw 0.1.1)
I've been recently using sigrok to acquire some data using an LCSoft CY7C68013A development board coupled with a custom CPLD board. At some point I noticed weird logic levels (i.e. far from 0V and 3.3V) on the PB0-PB7 pins, and I just realized they are being driven as outputs when acquisition ends, apparently with the same logic level they last saw as inputs.
I've double checked everything: during acquisition PB0-PB7 can be driven to either logic 0 or 1 with a simple pull-up or pull-down resistor. Once acquisition ends PB0-PB7 are being driven by the CY7C68013A as outputs and cannot be pulled to the opposite logic state with the resistor.
Needless to say this situation causes a bus contention if the input signals change after acquisition ends (which they most likely will), and is likely to cause electrical damage to the CY7C68013A PB0-PB7 pins, the logic buffer (if used) or the system under test.
1- Can someone else confirm the problem with any other CY7C68013A board? (see note).
2- Why is the firmware driving PB0-PB7 as outputs after acquisition ends?.
Note: if you are using one of these CY7C68013A based logic analyzers, they usually have a 74HC244 input buffer. In this case when you probe the signals between the 74HC244 and the CY7C68013A during acquisition you should see clean logic levels (i.e. very close to 0V for logic 0 and very close to 3.3V for logic 1). After acquisition if you change the inputs causing an electrical conflict between the 74HC244 outputs and the CY7C68013A PB0-PB7 pins now being driven as outputs, your should see weird voltage values that depend on the exact components your board has. For example in my case driving a logic 1 from the 74HC244 results in about 2V when that pin is connected to a PB pin that was sampling a logic 0 during acquisition and seems to be now driving a logic 0 output.

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I seem to have the same problem... I'm using a "barebone" CY7C68013A board without any drivers (i.e. the PBx pins are directly connected to the DUT). When one of the PB pins samples a "1", this level is output still after sampling.

Actually, I had the issue when I was preparing the ATMEGA32 SPI dumps: The SPI and the in-circuit programming pins are the same and I wasn't able to use the ATMEL programmer after capturing the SPI signals. I thought the SPI signals may have tripped up the programmer but seems above mentioned behaviour is the culprit.

I am no CY7C68013A expert but according to the datasheet Port B has tri state functionality => So it should be possible to set the pins before & after acquisition accordingly, we "only" need to find the correct place in the firmware...

Regards - Clemens