Signs V0.6.3 released

After months of bug-fixing and regression-testing a new signs release is available:

Signs 0.6.3
http://www.iti.uni-stuttgart.de/~bartscgr/signs/download

While the release focus is clearly on bugfixes, there are some feature improvements as well such as enhanced test bench support and improved netlist and simulator views. The VHDL compiler has support for subprograms now and elaboration of big designs is much faster because of improved context handling.

Internally the intermediate representation layer was cleaned up, so intermediate objects form a proper tree now.