Recent changes to Searchlight_Panel

Searchlight_Panel modified by TwinDad

TwinDad — Tue, 20 May 2014 01:59:58 -0000

--- v14
+++ v15
@@ -177,6 +177,14 @@

 The Core Module provides the core logic for the system. It is intended to be installed in a central location. It need not be in the operator panel. 

+The core module is (tentatively) based on the Atmel AT89C51CC03 (or equivalent) Microcontroller in the PLCC52 or VQFP64 package. Relevant features: 
+
+  * CAN Port (for OpenLCB) 
+  * UART Port (for remote LED display) 
+  * SPI Port (for Input and Output controllers) 
+
+The dual SPI ports will be created by generating separate SSn selects and sharing the MISO/MOSI/CLK IO. 
+
 ### Block Diagram

 [ none | 200px](File:SLP_CoreBoard.png_)

Searchlight_Panel modified by TwinDad

TwinDad — Tue, 20 May 2014 01:59:58 -0000

--- v13
+++ v14
@@ -173,6 +173,14 @@

 MC_TxD and MC_RxD are defined from the perspective of the primary microcontroller. That is, the LED controller transmits on RxD and receives on TxD. This convention is indicated by the "MC_" prefix. +5V is supplied by the primary controller, and is optional. The LED controller need not use it. 

+## Core Module Definition
+
+The Core Module provides the core logic for the system. It is intended to be installed in a central location. It need not be in the operator panel. 
+
+### Block Diagram
+
+[ none | 200px](File:SLP_CoreBoard.png_) 
+
 ## Input Module Definition

 The Input module provides the interface between the control panel switches and the main processor. It will also provide optional direct local LED feedback of the switch state.

Searchlight_Panel modified by TwinDad

TwinDad — Tue, 20 May 2014 01:59:58 -0000

--- v12
+++ v13
@@ -175,7 +175,7 @@

 ## Input Module Definition

-The Input module provides the interface between the control panel switches and the main processor. Optionally, it will provide direct local LED feedback of the switch state. 
+The Input module provides the interface between the control panel switches and the main processor. It will also provide optional direct local LED feedback of the switch state. 

 ### Block Diagram

@@ -185,23 +185,161 @@

 The Input Module provides connection for up to eight electrical switches for controlling eight turnouts (or turnout pairs), as well as LED indicator outputs for local panel indication. It is designed to be installed inside a control panel and connected to a master control processor via a ribbon cable. 

-The control bus connects via a bus transceiver to the board logic. A 4-DIP selects the board address, which the processor uses to read the switch settings. 
+The boards are connected in a "daisy chain" via a series of 6-pin ribbon cables. The underlying bus is SPI. 

 The switches are connected via a second ribbon cable (which can be separated for routing to the panel switches). Either SPDT or SPST switches can be used. For SPDT operation, the center lead of the switch is connected to the switch input, while +5V and GND are connected to the outer leads. When the switch is thrown, the board input is tied to +5V or GND, and the logic is able to read the switch position. For use with SPST switches, pullups to +5V are provided on the board. The switch is wired from the board input to GND, and the open position represents +5V. 

-By convention, +5V indicates the diverging turnout position (switch "thrown"), and GND indicates the "through" turnout position (switch "closed"). 
-
-The processor continually polls all the boards on the ribbon cable bus. When the Input Module detects its own address on the bus, it will drive the current state of the switches onto the bus (or read the value sent by the processor), as described above in the bus interface documentation. 
-
-Local panel LEDs are automatically driven by the input switch position. Exact implementation is TBD. 
-
-Each Input Module on the bus must be assigned a unique address value by setting the DIP switches on the board. 16 different addresses are available. The address value of each Input Module must also match the address of a corresponding Output Module, and the input pins and output pins matched to ensure that a given input switch triggers the correct turnout. 
-
-For example, one must wire such that Switch #2 on Input Module #3 is mated to the turnout on Output #2 on Output Module #3. 
-
-### Alternate Address Assignment Method
-
-I may choose to "daisy-chain" the input and output modules in such a way that the physical bus connections indicate the address numbers (first board in the chain is Address 1, and so on). At Power on, all the boards would disconnect their "downstream" bus connections. The processor then would go through a process of "discovering" and assigning addresses to each board in sequence. There are issues with this, though, and I'm not sure I want to go that way. 
+By convention, +5V indicates the diverging turnout position (turnout switch "thrown"), and GND indicates the "through" turnout position (turnout switch "closed"). 
+
+The Master processor continually polls all the boards on the ribbon cable bus. Each time the SSn signal is driven active (low), the Input Module will load the current state of its switches into its shift register. The Master processor will then clock out all of the switch conditions, and deassert SSn. 
+
+Local panel LEDs are automatically driven by the input switch position. 
+
+Due to the daisy-chain nature of the processor bus, a theoretically unlimited number of Input Boards can be connected. However, timing places a practical limit (TBD) on the number of supported boards. The Input Boards and Output Boards (and therefore the panel switch -> turnout relationship) are associated by their relative position in the daisy chain. 
+
+### Tenative Module BOM
+
+Item  Description  Mfg  P/N  Or Equiv?  Qty  Unit $  Net $  Notes 
+
+1 
+Core Logic CPLD 
+Xilinx 
+XC2C64A-VQ44 
+N 
+1 
+$2.45 
+$2.45 
+
+2 
+6x1 header 
+Molex 
+22-03-2061 
+Y 
+2 
+$0.74 
+$1.48 
+Bus connectors 
+
+3 
+4x1 header 
+Molex 
+22-03-4041 
+Y 
+1 
+$0.32 
+$0.32 
+JTAG Header 
+
+4 
+2x1 jumper 
+Molex 
+22-03-2021 
+Y 
+1 
+$0.44 
+$0.44 
+Bus Terminator 
+
+5 
+5x2 header 
+Molex 
+90131-0125 
+Y 
+1 
+$1.07 
+$1.07 
+Switch inputs 
+
+6 
+9x2 header 
+Molex 
+90131-0129 
+Y 
+1 
+$1.93 
+$1.93 
+LED outputs 
+
+7 
+74xx541 
+Fairchild 
+74LCX541WM 
+Y 
+2 
+$0.61 
+$1.22 
+LED drivers 
+
+8 
+220Ω RPAK-4 
+Vishay 
+CRA06S083220RJTA 
+Y 
+4 
+$0.023 
+$0.23 
+LED pullups (Min order 10) 
+
+9 
+5KΩ RPAK-4 
+Vishay 
+CRA06S0835K10JTA 
+Y 
+2 
+$0.023 
+$0.23 
+Switch pullups (Min order 10) 
+
+10 
+5KΩ Resistor 
+Panasonic 
+ERJ-3GEYJ512V 
+Y 
+1 
+$0.03 
+$0.03 
+Terminator pullup 
+
+11 
+10pF Cap 
+TDK 
+C1608C0G1H100D 
+Y 
+10? 
+$0.024 
+$0.24 
+isolation caps (Min order 10) 
+
+12 
+Clock Circuit (TBD) 
+TBD 
+TBD 
+Y 
+1 
+$$ 
+$$ 
+Design TBD 
+
+13 
+PCB 
+Sunstone 
+N/A 
+Y 
+1 
+$24.00 
+$18.00 
+Est 4x1.5 @ $3/sq.in. 
+
+14 
+PCB NRE 
+Sunstone 
+N/A 
+Y 
+1 
+$25.00 
+$25.00 
+
+Current total cost estimate per board = $27.41 + NRE + Clock circuit 

 ## Output Module Definition

Searchlight_Panel modified by TwinDad

TwinDad — Tue, 20 May 2014 01:59:57 -0000

--- v11
+++ v12
@@ -81,6 +81,8 @@
 For expandability, all slaves will have 16 bit SPI bus ports. Unconnected ports will always return '0'.

 ### Output Control Bus
+
+**NOTE: This bus, like the Input bus, is about to receive an overhaul to a SPI based serial interface with fewer pins.**

 This bus runs from the microcontroller to the output modules. Each output module has an assigned address, and responds only if the address lines match its address. This bus is clocked. Changes are only made on the rising edge of the CLK line (which is really a latch enable).

Searchlight_Panel modified by TwinDad

TwinDad — Tue, 20 May 2014 01:59:57 -0000

--- v10
+++ v11
@@ -46,9 +46,13 @@

 ### Switch input bus

-The switch input bus is a 16-pin ribbon cable that connects all of the switch input boards in parallel to the microcontroller. Each switch input board provides 8 inputs, and has a unique bus address (set by DIP switches on the board). The bus is an 8-bit data, 4-bit address bus allowing up to 16 boards, or 128 switches. 
-
-The bus is clocked, and operates in a simple master-slave relationship. The processor (master) sets the address and R/W bits, and pulses the CLK. At the CLK high, the input board either latches the value on the DATA lines (R/W == W) or drives the value of its input pins onto the DATA lines (R/W == R). When CLK falls, the input board reverts the DATA lines to a tri-state condition. 
+(News: After toying with the logic required to implement a daisy-chained SPI bus, I'm going with what was Alternate 2) 
+
+The switch input bus is a 6-pin ribbon cable that connects all of the switch input boards to the microcontroller. The microcontroller has a user setting on the board that tells it how many input boards are connected. All of the input boards are in a daisy-chain, so the master simply clocks all the pin data through the chain to collect it. 
+
+Alternately, the slaves can all power up to a "all zeroes" state, and the master can clock a magic word through the chain in order to measure its length at runtime. Once this is complete, the master can clock a reset value out that will cause the input boards to load their switch states onto the bus. This would eliminate the need for a user setting on the bus size. 
+
+Logic HIGH indicates diverging route (switch is thrown), LOW indicates main line route (switch is closed). 

 Pin  Description 

@@ -56,62 +60,6 @@
 +5V 

 2 
-DATA_0 
-
-3 
-DATA_1 
-
-4 
-DATA_2 
-
-5 
-DATA_3 
-
-6 
-DATA_4 
-
-7 
-DATA_5 
-
-8 
-DATA_6 
-
-9 
-DATA_7 
-
-10 
-Addr 0 
-
-11 
-Addr 1 
-
-12 
-Addr 2 
-
-13 
-Addr 3 
-
-14 
-CLK 
-
-15 
-R/W 
-
-16 
-GND 
-
-Logic HIGH indicates diverging route (switch is thrown), LOW indicates main line route (switch is closed). 
-
-#### Alternate 1: SPI-bus
-
-A lower-pin-count alternate is a SPI-bus based design, still with multi-bit decoded addressing: 
-
-Pin  Description 
-
-1 
-+5V 
-
-2 
 MISO 

 3 
@@ -121,72 +69,16 @@
 SCLK 

 5 
-GND 
+SSn 

 6 
-Addr 0 
-
-7 
-Addr 1 
-
-8 
-Addr 2 
-
-9 
-Addr 3 
-
-10 
-GND 
-
-This version still supports 16 boards (total 128 switches), but does so with only a 10-wire cable, instead of 16. Typically, SPI uses separate chip selects for each slave. That would be a bit of a mess here. Since I'm using custom-made slave devices, the chip select will be decoded by the slave on-board. To connect a "standard" SPI slave (whatever that is), an address decoder (and some form of assigning an address) would have to be added to that slave, but it would otherwise work as expected. 
-
-Pros: 
-
-  * Lower pin count than parallel 
-
-Cons: 
-
-  * Still requires setting addresses on the boards 
-
-#### Alternate 2: Daisy Chain SPI
-
-An even smaller bus can be configured, if the Master device can be told how many slave devices are installed, so it knows how many bits to shift out. This could be done with a DIP switch or rotary encoder on the master board. 
-
-Pin  Description 
-
-1 
-+5V 
-
-2 
-MISO 
-
-3 
-MOSI 
-
-4 
-SCLK 
-
-5 
-SSn 
-
-6 
 GND 

 In this case, the boards are all connected in daisy chain fashion (each board's MOSI is the next board's MOSI). The master clocks however many bits it expects to see (as indicated by the "how many boards" setting). If there are 4 boards installed, the master will clock 32 bits, and gather the switch states of all 4 boards in one read. 

-The daisy chain can be single-ended if the last board has a jumper set or installed to loop back the return path (I think) 
-
-Pros: 
-
-  * 6-conductor cable 
-  * No need for assigning addresses to the slave devices 
-
-Cons: 
-
-  * Must correctly set the number of attached slaves on the master 
-  * Must correctly assemble the daisy chain 
-  * Requires two connectors on each board, and some sort of termination if a loop is not used. 
-  * All slaves must have the same bit width, and "big slaves" must be counted as 2 devices on the master. 
+The daisy chain can be single-ended if the last board has a jumper set or installed to loop back the return path. 
+
+For expandability, all slaves will have 16 bit SPI bus ports. Unconnected ports will always return '0'. 

 ### Output Control Bus

Searchlight_Panel modified by TwinDad

TwinDad — Tue, 20 May 2014 01:59:57 -0000

--- v9
+++ v10
@@ -167,6 +167,9 @@
 SCLK

 5 
+SSn 
+
+6 
 GND 

 In this case, the boards are all connected in daisy chain fashion (each board's MOSI is the next board's MOSI). The master clocks however many bits it expects to see (as indicated by the "how many boards" setting). If there are 4 boards installed, the master will clock 32 bits, and gather the switch states of all 4 boards in one read. 
@@ -175,7 +178,7 @@

 Pros: 

-  * 5-conductor cable 
+  * 6-conductor cable 
   * No need for assigning addresses to the slave devices 

 Cons:

Searchlight_Panel modified by TwinDad

TwinDad — Tue, 20 May 2014 01:59:57 -0000

--- v8
+++ v9
@@ -101,6 +101,89 @@
 GND

 Logic HIGH indicates diverging route (switch is thrown), LOW indicates main line route (switch is closed). 
+
+#### Alternate 1: SPI-bus
+
+A lower-pin-count alternate is a SPI-bus based design, still with multi-bit decoded addressing: 
+
+Pin  Description 
+
+1 
++5V 
+
+2 
+MISO 
+
+3 
+MOSI 
+
+4 
+SCLK 
+
+5 
+GND 
+
+6 
+Addr 0 
+
+7 
+Addr 1 
+
+8 
+Addr 2 
+
+9 
+Addr 3 
+
+10 
+GND 
+
+This version still supports 16 boards (total 128 switches), but does so with only a 10-wire cable, instead of 16. Typically, SPI uses separate chip selects for each slave. That would be a bit of a mess here. Since I'm using custom-made slave devices, the chip select will be decoded by the slave on-board. To connect a "standard" SPI slave (whatever that is), an address decoder (and some form of assigning an address) would have to be added to that slave, but it would otherwise work as expected. 
+
+Pros: 
+
+  * Lower pin count than parallel 
+
+Cons: 
+
+  * Still requires setting addresses on the boards 
+
+#### Alternate 2: Daisy Chain SPI
+
+An even smaller bus can be configured, if the Master device can be told how many slave devices are installed, so it knows how many bits to shift out. This could be done with a DIP switch or rotary encoder on the master board. 
+
+Pin  Description 
+
+1 
++5V 
+
+2 
+MISO 
+
+3 
+MOSI 
+
+4 
+SCLK 
+
+5 
+GND 
+
+In this case, the boards are all connected in daisy chain fashion (each board's MOSI is the next board's MOSI). The master clocks however many bits it expects to see (as indicated by the "how many boards" setting). If there are 4 boards installed, the master will clock 32 bits, and gather the switch states of all 4 boards in one read. 
+
+The daisy chain can be single-ended if the last board has a jumper set or installed to loop back the return path (I think) 
+
+Pros: 
+
+  * 5-conductor cable 
+  * No need for assigning addresses to the slave devices 
+
+Cons: 
+
+  * Must correctly set the number of attached slaves on the master 
+  * Must correctly assemble the daisy chain 
+  * Requires two connectors on each board, and some sort of termination if a loop is not used. 
+  * All slaves must have the same bit width, and "big slaves" must be counted as 2 devices on the master. 

 ### Output Control Bus

Searchlight_Panel modified by TwinDad

TwinDad — Tue, 20 May 2014 01:59:57 -0000

--- v7
+++ v8
@@ -203,7 +203,25 @@

 ### Functional Description

-Blah 
+The Input Module provides connection for up to eight electrical switches for controlling eight turnouts (or turnout pairs), as well as LED indicator outputs for local panel indication. It is designed to be installed inside a control panel and connected to a master control processor via a ribbon cable. 
+
+The control bus connects via a bus transceiver to the board logic. A 4-DIP selects the board address, which the processor uses to read the switch settings. 
+
+The switches are connected via a second ribbon cable (which can be separated for routing to the panel switches). Either SPDT or SPST switches can be used. For SPDT operation, the center lead of the switch is connected to the switch input, while +5V and GND are connected to the outer leads. When the switch is thrown, the board input is tied to +5V or GND, and the logic is able to read the switch position. For use with SPST switches, pullups to +5V are provided on the board. The switch is wired from the board input to GND, and the open position represents +5V. 
+
+By convention, +5V indicates the diverging turnout position (switch "thrown"), and GND indicates the "through" turnout position (switch "closed"). 
+
+The processor continually polls all the boards on the ribbon cable bus. When the Input Module detects its own address on the bus, it will drive the current state of the switches onto the bus (or read the value sent by the processor), as described above in the bus interface documentation. 
+
+Local panel LEDs are automatically driven by the input switch position. Exact implementation is TBD. 
+
+Each Input Module on the bus must be assigned a unique address value by setting the DIP switches on the board. 16 different addresses are available. The address value of each Input Module must also match the address of a corresponding Output Module, and the input pins and output pins matched to ensure that a given input switch triggers the correct turnout. 
+
+For example, one must wire such that Switch #2 on Input Module #3 is mated to the turnout on Output #2 on Output Module #3. 
+
+### Alternate Address Assignment Method
+
+I may choose to "daisy-chain" the input and output modules in such a way that the physical bus connections indicate the address numbers (first board in the chain is Address 1, and so on). At Power on, all the boards would disconnect their "downstream" bus connections. The processor then would go through a process of "discovering" and assigning addresses to each board in sequence. There are issues with this, though, and I'm not sure I want to go that way. 

 ## Output Module Definition

Searchlight_Panel modified by TwinDad

TwinDad — Tue, 20 May 2014 01:59:56 -0000

--- v6
+++ v7
@@ -192,3 +192,23 @@
 GND

 MC_TxD and MC_RxD are defined from the perspective of the primary microcontroller. That is, the LED controller transmits on RxD and receives on TxD. This convention is indicated by the "MC_" prefix. +5V is supplied by the primary controller, and is optional. The LED controller need not use it. 
+
+## Input Module Definition
+
+The Input module provides the interface between the control panel switches and the main processor. Optionally, it will provide direct local LED feedback of the switch state. 
+
+### Block Diagram
+
+[ none | 100px](Image:SLP_InputBoard.png_) 
+
+### Functional Description
+
+Blah 
+
+## Output Module Definition
+
+### Block Diagram
+
+[ none | 100px](Image:SLP_OutputBoard.png_) 
+
+### Functional Description

Searchlight_Panel modified by TwinDad

TwinDad — Tue, 20 May 2014 01:59:56 -0000

--- v5
+++ v6
@@ -108,9 +108,16 @@

 The bus transaction appears as follows: 

-1\. Processor places Output Module address on BD_ADDR 2\. Processor places TO Number (encoded) on OP_ADDR 3\. Processor pulses CLK. 
+  1. Processor places Output Module address on BD_ADDR 
+  2. Processor places TO Number (encoded) on OP_ADDR 
+  3. Processor pulses CLK high. 
+  4. Output Module connects CDU to the selected switch output 
+  5. CDU pulse completes 
+  6. Output Module disconnects all switch outputs from the CDU 

 When CLK is driven high, the CDU output is routed to the appropriate turnout output. When CLK goes low, all outputs are disconnected from the CDU. 
+
+A "digital safe" version of the CDU pulse is returned to the processor via the CDU_FB pin, for timing. The processor will not issue another pulse until a specified recharge time after the previous pulse. 

 Alt: A "digital safe" version of the CDU pulse is routed as an input to the module logic, and the outputs are not disconnected until the pulse itself is finished. This makes the clock rising-edge-only. 

@@ -156,7 +163,7 @@
 CLK 

 14 
-GND 
+CDU_FB 

 15 
 GND