Recent changes to NGI0-Entrust-SDCC

NGI0-Entrust-SDCC modified by Philipp Klaus Krause

Philipp Klaus Krause — Wed, 25 Jun 2025 05:40:13 -0000

NGI0-SDCC modified by Philipp Klaus Krause

Philipp Klaus Krause — Fri, 05 Jul 2024 09:35:17 -0000

--- v37
+++ v38
@@ -1,4 +1,7 @@
 NLnet is funding an NGI0 "[SDCC](https://nlnet.nl/project/SDCC/)" project done by @spth and @felixs. NLnet manages the NGI0 Entrust fund, which was established with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101069594.
+
+[[[img src=NGI0Entrust_tag.svg alt="NGI0 Entrust" width=200]]](https://nlnet.nl/NGI0/)
+

 Monthly progress reports
 ==

NGI0-SDCC modified by Philipp Klaus Krause

Philipp Klaus Krause — Mon, 01 Apr 2024 10:34:26 -0000

--- v36
+++ v37
@@ -35,5 +35,5 @@

 **February:** I mostly worked on the Verilog model of the single-cycle f8 core. It is now reasonably complete, each instruction works in a small test program with the core simulated in Icarus. It was nearly there already last year, but the last few instructions still took quite some effort. Actually, most of my time was spend on fixing interrupt handling.

-**March:**: Due to its mature free toolchain, I went with a Lattice iCE40 as first target; when I needed more memory, I looked into the CologneChips GateMate. The f8 Verilog code now synthesizes for the iCE40UP5K and GateMateA1 FPGAs. Post-synthesis tests pass for the iCE40UP5K. For the GateMateA1, there are some test failures, but it looks like this might be a problem in yosys, and I'm in contact with the authors of the synth_gatemate pass in yosys to look into it. Two simple demos (LED blinking and "Hellor, world!" output via software-emulated UART) work on both the iCEBreaker and GateMateA1-EVB boards. However, there are still serious issues: Dhrystone on the GateMateA1-EVB crashes after the first three lines of output. Also, this is my very first nontrivial Verilog design, and it shows. It is big and slow (about 5 MHz on the iCE40UP5K). In retrospective, going for a single-cycle core probably wasn't a good choice for the f8 with its many read-modify-write instructions. The single-cycle approach required a program memory with multiple read ports (which the iCE40 doesn't have), which now looks like too much to demand for an 8bit architecture, that is meant to fill the gap below 32-bit CPUs,such as RISC-V. For now, my f8 implementation is both bigger and slower than a minimal RISC-V.
+**March:** Due to its mature free toolchain, I went with a Lattice iCE40 as first target; when I needed more memory, I looked into the CologneChips GateMate. The f8 Verilog code now synthesizes for the iCE40UP5K and GateMateA1 FPGAs. Post-synthesis tests pass for the iCE40UP5K. For the GateMateA1, there are some test failures, but it looks like this might be a problem in yosys, and I'm in contact with the authors of the synth_gatemate pass in yosys to look into it. Two simple demos (LED blinking and "Hellor, world!" output via software-emulated UART) work on both the iCEBreaker and GateMateA1-EVB boards. However, there are still serious issues: Dhrystone on the GateMateA1-EVB crashes after the first three lines of output. Also, this is my very first nontrivial Verilog design, and it shows. It is big and slow (about 5 MHz on the iCE40UP5K). In retrospective, going for a single-cycle core probably wasn't a good choice for the f8 with its many read-modify-write instructions. The single-cycle approach required a program memory with multiple read ports (which the iCE40 doesn't have), which now looks like too much to demand for an 8bit architecture, that is meant to fill the gap below 32-bit CPUs,such as RISC-V. For now, my f8 implementation is both bigger and slower than a minimal RISC-V.
 This was the last month of this project. For the f8, there is already a follow-up project: [NGI0-f8], giving me a chance to do better.

NGI0-SDCC modified by Philipp Klaus Krause

Philipp Klaus Krause — Mon, 01 Apr 2024 08:13:54 -0000

--- v35
+++ v36
@@ -34,3 +34,6 @@
 **January:** A few more issues in the release candiates were found and fixes, but we finally released SDCC 4.4.0, finally bringing all the optimizations and bugfixes I worked on since mid-2023 to SDCC users . Otherwise, there wasn't much progress on this project, though.

 **February:** I mostly worked on the Verilog model of the single-cycle f8 core. It is now reasonably complete, each instruction works in a small test program with the core simulated in Icarus. It was nearly there already last year, but the last few instructions still took quite some effort. Actually, most of my time was spend on fixing interrupt handling.
+
+**March:**: Due to its mature free toolchain, I went with a Lattice iCE40 as first target; when I needed more memory, I looked into the CologneChips GateMate. The f8 Verilog code now synthesizes for the iCE40UP5K and GateMateA1 FPGAs. Post-synthesis tests pass for the iCE40UP5K. For the GateMateA1, there are some test failures, but it looks like this might be a problem in yosys, and I'm in contact with the authors of the synth_gatemate pass in yosys to look into it. Two simple demos (LED blinking and "Hellor, world!" output via software-emulated UART) work on both the iCEBreaker and GateMateA1-EVB boards. However, there are still serious issues: Dhrystone on the GateMateA1-EVB crashes after the first three lines of output. Also, this is my very first nontrivial Verilog design, and it shows. It is big and slow (about 5 MHz on the iCE40UP5K). In retrospective, going for a single-cycle core probably wasn't a good choice for the f8 with its many read-modify-write instructions. The single-cycle approach required a program memory with multiple read ports (which the iCE40 doesn't have), which now looks like too much to demand for an 8bit architecture, that is meant to fill the gap below 32-bit CPUs,such as RISC-V. For now, my f8 implementation is both bigger and slower than a minimal RISC-V.
+This was the last month of this project. For the f8, there is already a follow-up project: [NGI0-f8], giving me a chance to do better.

NGI0-SDCC modified by Philipp Klaus Krause

Philipp Klaus Krause — Mon, 18 Mar 2024 19:41:23 -0000

--- v34
+++ v35
@@ -1,4 +1,4 @@
-NLnet is funding an NGI0 "[SDCC](https://nlnet.nl/project/SDCC/)" project done by @spth and | @felixs. NLnet manages the NGI0 Entrust fund, which was established with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101069594.
+NLnet is funding an NGI0 "[SDCC](https://nlnet.nl/project/SDCC/)" project done by @spth and @felixs. NLnet manages the NGI0 Entrust fund, which was established with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101069594.

 Monthly progress reports
 ==
@@ -33,4 +33,4 @@

 **January:** A few more issues in the release candiates were found and fixes, but we finally released SDCC 4.4.0, finally bringing all the optimizations and bugfixes I worked on since mid-2023 to SDCC users . Otherwise, there wasn't much progress on this project, though.

-**February:** I mostly worked on the Verilog model of the single-cycle f8 core. It is now reasonably complete, each instruction works in a small test program with the core simulated in Icarus. It was nearly there already last year, but he last few instructions still took quite some effort. Actually, most of my time was spend on fixing interrupt handling.
+**February:** I mostly worked on the Verilog model of the single-cycle f8 core. It is now reasonably complete, each instruction works in a small test program with the core simulated in Icarus. It was nearly there already last year, but the last few instructions still took quite some effort. Actually, most of my time was spend on fixing interrupt handling.

NGI0-SDCC modified by Philipp Klaus Krause

Philipp Klaus Krause — Mon, 18 Mar 2024 14:27:47 -0000

--- v33
+++ v34
@@ -1,4 +1,4 @@
-NLnet is funding an NGI0 "[SDCC](https://nlnet.nl/project/SDCC/)" project done by @spth. NLnet manages the NGI0 Entrust fund, which was established with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101069594.
+NLnet is funding an NGI0 "[SDCC](https://nlnet.nl/project/SDCC/)" project done by @spth and | @felixs. NLnet manages the NGI0 Entrust fund, which was established with financial support from the European Commission's Next Generation Internet programme, under the aegis of DG Communications Networks, Content and Technology under grant agreement No 101069594.

 Monthly progress reports
 ==

NGI0-SDCC modified by Philipp Klaus Krause

Philipp Klaus Krause — Thu, 29 Feb 2024 09:04:16 -0000

--- v32
+++ v33
@@ -32,3 +32,5 @@
 **December:** Sorry for the late update. There was no real progress on the NGI0 project in December. Instead the focus was on working towards the SDCC 4.4.0 release with bugfixes; by 2023-12-21, we had SDCC 4.4.0 RC1.

 **January:** A few more issues in the release candiates were found and fixes, but we finally released SDCC 4.4.0, finally bringing all the optimizations and bugfixes I worked on since mid-2023 to SDCC users . Otherwise, there wasn't much progress on this project, though.
+
+**February:** I mostly worked on the Verilog model of the single-cycle f8 core. It is now reasonably complete, each instruction works in a small test program with the core simulated in Icarus. It was nearly there already last year, but he last few instructions still took quite some effort. Actually, most of my time was spend on fixing interrupt handling.

NGI0-SDCC modified by Philipp Klaus Krause

Philipp Klaus Krause — Thu, 01 Feb 2024 08:46:54 -0000

--- v31
+++ v32
@@ -30,3 +30,5 @@
 **November:** This month I didn't find much time to work on the project. Basically, I did some small improvements to generalized constant propagation (fixed a bug that resulted in some optimizations on bit-wide operations being omitted, implemented optimizations for code generation for shifts for some backends). By far most of the work I did on SDCC this month was outside this project (bugfixing to prepare for the 4.4.0 release, setting up the new aarch64 machine and getting it into the compile farm, improved code speed optimizations for the z80 and related ports). I hope to find time to really get back to the f8 work early next month.

 **December:** Sorry for the late update. There was no real progress on the NGI0 project in December. Instead the focus was on working towards the SDCC 4.4.0 release with bugfixes; by 2023-12-21, we had SDCC 4.4.0 RC1.
+
+**January:** A few more issues in the release candiates were found and fixes, but we finally released SDCC 4.4.0, finally bringing all the optimizations and bugfixes I worked on since mid-2023 to SDCC users . Otherwise, there wasn't much progress on this project, though.

NGI0-SDCC modified by Philipp Klaus Krause

Philipp Klaus Krause — Thu, 18 Jan 2024 07:48:12 -0000

--- v30
+++ v31
@@ -28,3 +28,5 @@
 Finally, what I believe to have been the last serious issues in generalized constant propagation have been fixed; snapshots build, regression test results look good. We now see a lot more green dots on https://sdcc.sourceforge.net/snap.php than at the beginning of the month. There are  a few serious bugs left that needed fixing before we can do the next major release, but I am optimistic about progress. Meanwhile, the focus of this project will shift back to the f8.

 **November:** This month I didn't find much time to work on the project. Basically, I did some small improvements to generalized constant propagation (fixed a bug that resulted in some optimizations on bit-wide operations being omitted, implemented optimizations for code generation for shifts for some backends). By far most of the work I did on SDCC this month was outside this project (bugfixing to prepare for the 4.4.0 release, setting up the new aarch64 machine and getting it into the compile farm, improved code speed optimizations for the z80 and related ports). I hope to find time to really get back to the f8 work early next month.
+
+**December:** Sorry for the late update. There was no real progress on the NGI0 project in December. Instead the focus was on working towards the SDCC 4.4.0 release with bugfixes; by 2023-12-21, we had SDCC 4.4.0 RC1.

NGI0-SDCC modified by Philipp Klaus Krause

Philipp Klaus Krause — Wed, 29 Nov 2023 09:40:27 -0000

--- v29
+++ v30
@@ -26,3 +26,5 @@

 **October:** We ran out of in-project bugfixing hours months ago, so there is not much point continuing to record those. Of course I still fix bugs, but for quite a while that bugfixing hasn't been part of this project, so starting with this report I won't list any details or hours for that. The powerpc64 machine is in the compile farm now (running GNU/Linux, not the originally intended OpenBSD, which turned out to be far too slow), and the GNU/Linux aarch64 machine will soon be replaced by a faster one.
 Finally, what I believe to have been the last serious issues in generalized constant propagation have been fixed; snapshots build, regression test results look good. We now see a lot more green dots on https://sdcc.sourceforge.net/snap.php than at the beginning of the month. There are  a few serious bugs left that needed fixing before we can do the next major release, but I am optimistic about progress. Meanwhile, the focus of this project will shift back to the f8.
+
+**November:** This month I didn't find much time to work on the project. Basically, I did some small improvements to generalized constant propagation (fixed a bug that resulted in some optimizations on bit-wide operations being omitted, implemented optimizations for code generation for shifts for some backends). By far most of the work I did on SDCC this month was outside this project (bugfixing to prepare for the 4.4.0 release, setting up the new aarch64 machine and getting it into the compile farm, improved code speed optimizations for the z80 and related ports). I hope to find time to really get back to the f8 work early next month.