#26 Reporting Problem for Cygnal C8051F020
Hi All,
As Maarten suggested me, I'm reporting problem i have
using sdcc with mcu Cygnal 8051F020.
I currently using and working with sdcc version 2.3.3
(March 3 2003). The Problem is that I cannot use any
versions following the sdcc dated March 3 2003 on the
Cygnal 8051F020. I can compile with any sdcc version.
So I obtain a .ihx file. But, after downloading it, I never
come into main().
Probable It is a problem into startup code.
With sdcc version 2.3.3 I can compile and i can debug
using the Cygnal IDE and the jtag Serial Adapter.
Before Starting coding activity I developped a
reg8051F020.h file as stamped below (using originals file
from J.R. Wittrock). Can I propose to add it to the
sdcc/include folder. If the file is right, Is It Possible?
//-----------------------------------------------------
-------------------------
//
//FILE : reg51F020.h
//DESCRIPTION : Register descriptions for
Cygnal C51F020/1/2/3 MCU
// : (adapted from cygnal IDE Compiter
for
// : SDCC free Compiler for PIC,Z80,8051)
//REVISION : 0.0
//AUTHOR : W. Frasson - J.R. Wittrock
//NOTES : sbit definitions changed
for compatibility with SDCC
// : sfr16 removed for
compatibility with SDCC
// : Usage:
// : To use KEIL COMPILER
uncomment KEIL_COMPILER flag.
// : To use SDCC COMPILER
uncomment the SDCC_COMPIER flag.
//CHANGE LOG: : 20/07/2003 First Issue
// :
// :
//-----------------------------------------------------
-------------------------
#ifndef __REG51F020_H__
#define __REG51F020_H__
//-----------------------------------------------------
-------------------------
//-- C8051F020 MCU BYTE Registers
//-----------------------------------------------------
-------------------------
sfr P0 = 0x80; /* PORT 0 */
sfr SP = 0x81; /* STACK
POINTER */
sfr DPL = 0x82; /* DATA POINTER - LOW
BYTE */
sfr DPH = 0x83; /* DATA POINTER - HIGH
BYTE */
sfr P4 = 0x84; /* PORT 4
*/
sfr P5 = 0x85; /* PORT
5 */
sfr P6 = 0x86; /* PORT 6
*/
sfr PCON = 0x87; /* POWER
CONTROL */
sfr TCON = 0x88; /* TIMER
CONTROL */
sfr TMOD = 0x89; /* TIMER
MODE */
sfr TL0 = 0x8A; /* TIMER 0 - LOW
BYTE */
sfr TL1 = 0x8B; /* TIMER 1 - LOW
BYTE */
sfr TH0 = 0x8C; /* TIMER 0 - HIGH
BYTE */
sfr TH1 = 0x8D; /* TIMER 1 - HIGH
BYTE */
sfr CKCON = 0x8E; /* CLOCK
CONTROL */
sfr PSCTL = 0x8F; /* PROGRAM STORE R/W
CONTROL */
sfr P1 = 0x90; /* PORT
1 */
sfr TMR3CN = 0x91; /* TIMER 3
CONTROL */
sfr TMR3RLL = 0x92; /* TIMER 3 RELOAD
REGISTER - LOW BYTE */
sfr TMR3RLH = 0x93; /* TIMER 3 RELOAD
REGISTER - HIGH BYTE */
sfr TMR3L = 0x94; /* TIMER 3 - LOW
BYTE */
sfr TMR3H = 0x95; /* TIMER 3 - HIGH
BYTE */
sfr P7 = 0x96; /* PORT
7 */
sfr SCON0 = 0x98; /* SERIAL PORT 0
CONTROL */
sfr SBUF0 = 0x99; /* SERIAL PORT 0
BUFFER */
sfr SPI0CFG = 0x9A; /* SERIAL PERIPHERAL
INTERFACE 0 CONFIGURATION */
sfr SPI0DAT = 0x9B; /* SERIAL PERIPHERAL
INTERFACE 0 DATA */
sfr ADC1 = 0x9C; /* ADC 1
DATA */
sfr SPI0CKR = 0x9D; /* SERIAL PERIPHERAL
INTERFACE 0 CLOCK RATE CONTROL */
sfr CPT0CN = 0x9E; /* COMPARATOR 0
CONTROL */
sfr CPT1CN = 0x9F; /* COMPARATOR 1
CONTROL */
sfr P2 = 0xA0; /* PORT
2 */
sfr EMI0TC = 0xA1; /* EMIF TIMING
CONTROL */
sfr EMI0CF = 0xA3; /* EXTERNAL MEMORY
INTERFACE (EMIF) CONFIGURATION */
sfr P0MDOUT = 0xA4; /* PORT 0 OUTPUT MODE
CONFIGURATION */
sfr P1MDOUT = 0xA5; /* PORT 1 OUTPUT MODE
CONFIGURATION */
sfr P2MDOUT = 0xA6; /* PORT 2 OUTPUT MODE
CONFIGURATION */
sfr P3MDOUT = 0xA7; /* PORT 3 OUTPUT MODE
CONFIGURATION */
sfr IE = 0xA8; /* INTERRUPT
ENABLE */
sfr SADDR0 = 0xA9; /* SERIAL PORT 0 SLAVE
ADDRESS */
sfr ADC1CN = 0xAA; /* ADC 1
CONTROL */
sfr ADC1CF = 0xAB; /* ADC 1 ANALOG MUX
CONFIGURATION */
sfr AMX1SL = 0xAC; /* ADC 1 ANALOG MUX CHANNEL
SELECT */
sfr P3IF = 0xAD; /* PORT 3 EXTERNAL INTERRUPT
FLAGS */
sfr SADEN1 = 0xAE; /* SERIAL PORT 1 SLAVE
ADDRESS MASK */
sfr EMI0CN = 0xAF; /* EXTERNAL MEMORY
INTERFACE CONTROL */
sfr P3 = 0xB0; /* PORT
3 */
sfr OSCXCN = 0xB1; /* EXTERNAL OSCILLATOR
CONTROL */
sfr OSCICN = 0xB2; /* INTERNAL OSCILLATOR
CONTROL */
sfr P74OUT = 0xB5; /* PORTS 4 - 7 OUTPUT
MODE */
sfr FLSCL = 0xB6; /* FLASH MEMORY TIMING
PRESCALER */
sfr FLACL = 0xB7; /* FLASH ACESS
LIMIT */
sfr IP = 0xB8; /* INTERRUPT
PRIORITY */
sfr SADEN0 = 0xB9; /* SERIAL PORT 0 SLAVE
ADDRESS MASK */
sfr AMX0CF = 0xBA; /* ADC 0 MUX
CONFIGURATION */
sfr AMX0SL = 0xBB; /* ADC 0 MUX CHANNEL
SELECTION */
sfr ADC0CF = 0xBC; /* ADC 0
CONFIGURATION */
sfr P1MDIN = 0xBD; /* PORT 1 INPUT
MODE */
sfr ADC0L = 0xBE; /* ADC 0 DATA - LOW
BYTE */
sfr ADC0H = 0xBF; /* ADC 0 DATA - HIGH
BYTE */
sfr SMB0CN = 0xC0; /* SMBUS 0
CONTROL */
sfr SMB0STA = 0xC1; /* SMBUS 0
STATUS */
sfr SMB0DAT = 0xC2; /* SMBUS 0
DATA */
sfr SMB0ADR = 0xC3; /* SMBUS 0 SLAVE
ADDRESS */
sfr ADC0GTL = 0xC4; /* ADC 0 GREATER-THAN
REGISTER - LOW BYTE */
sfr ADC0GTH = 0xC5; /* ADC 0 GREATER-THAN
REGISTER - HIGH BYTE */
sfr ADC0LTL = 0xC6; /* ADC 0 LESS-THAN
REGISTER - LOW BYTE */
sfr ADC0LTH = 0xC7; /* ADC 0 LESS-THAN
REGISTER - HIGH BYTE */
sfr T2CON = 0xC8; /* TIMER 2
CONTROL */
sfr T4CON = 0xC9; /* TIMER 4
CONTROL */
sfr RCAP2L = 0xCA; /* TIMER 2 CAPTURE
REGISTER - LOW BYTE */
sfr RCAP2H = 0xCB; /* TIMER 2 CAPTURE
REGISTER - HIGH BYTE */
sfr TL2 = 0xCC; /* TIMER 2 - LOW
BYTE */
sfr TH2 = 0xCD; /* TIMER 2 - HIGH
BYTE */
sfr SMB0CR = 0xCF; /* SMBUS 0 CLOCK
RATE */
sfr PSW = 0xD0; /* PROGRAM STATUS
WORD */
sfr REF0CN = 0xD1; /* VOLTAGE REFERENCE 0
CONTROL */
sfr DAC0L = 0xD2; /* DAC 0 REGISTER - LOW
BYTE */
sfr DAC0H = 0xD3; /* DAC 0 REGISTER - HIGH
BYTE */
sfr DAC0CN = 0xD4; /* DAC 0
CONTROL */
sfr DAC1L = 0xD5; /* DAC 1 REGISTER - LOW
BYTE */
sfr DAC1H = 0xD6; /* DAC 1 REGISTER - HIGH
BYTE */
sfr DAC1CN = 0xD7; /* DAC 1
CONTROL */
sfr PCA0CN = 0xD8; /* PCA 0 COUNTER
CONTROL */
sfr PCA0MD = 0xD9; /* PCA 0 COUNTER
MODE */
sfr PCA0CPM0 = 0xDA; /* CONTROL REGISTER FOR
PCA 0 MODULE 0 */
sfr PCA0CPM1 = 0xDB; /* CONTROL REGISTER FOR
PCA 0 MODULE 1 */
sfr PCA0CPM2 = 0xDC; /* CONTROL REGISTER FOR
PCA 0 MODULE 2 */
sfr PCA0CPM3 = 0xDD; /* CONTROL REGISTER FOR
PCA 0 MODULE 3 */
sfr PCA0CPM4 = 0xDE; /* CONTROL REGISTER FOR
PCA 0 MODULE 4 */
sfr ACC = 0xE0; /*
ACCUMULATOR */
sfr XBR0 = 0xE1; /* DIGITAL CROSSBAR
CONFIGURATION REGISTER 0 */
sfr XBR1 = 0xE2; /* DIGITAL CROSSBAR
CONFIGURATION REGISTER 1 */
sfr XBR2 = 0xE3; /* DIGITAL CROSSBAR
CONFIGURATION REGISTER 2 */
sfr RCAP4L = 0xE4; /* TIMER 4 CAPTURE REGISTER -
LOW BYTE */
sfr RCAP4H = 0xE5; /* TIMER 4 CAPTURE REGISTER -
HIGH BYTE */
sfr EIE1 = 0xE6; /* EXTERNAL INTERRUPT
ENABLE 1 */
sfr EIE2 = 0xE7; /* EXTERNAL INTERRUPT
ENABLE 2 */
sfr ADC0CN = 0xE8; /* ADC 0
CONTROL */
sfr PCA0L = 0xE9; /* PCA 0 TIMER - LOW
BYTE */
sfr PCA0CPL0 = 0xEA; /* CAPTURE/COMPARE
REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
sfr PCA0CPL1 = 0xEB; /* CAPTURE/COMPARE
REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
sfr PCA0CPL2 = 0xEC; /* CAPTURE/COMPARE
REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
sfr PCA0CPL3 = 0xED; /* CAPTURE/COMPARE
REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
sfr PCA0CPL4 = 0xEE; /* CAPTURE/COMPARE
REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
sfr RSTSRC = 0xEF; /* RESET
SOURCE */
sfr B = 0xF0; /* B
REGISTER */
sfr SCON1 = 0xF1; /* SERIAL PORT 1
CONTROL */
sfr SBUF1 = 0xF2; /* SERAIL PORT 1
DATA */
sfr SADDR1 = 0xF3; /* SERAIL PORT
1 */
sfr TL4 = 0xF4; /* TIMER 4 DATA - LOW
BYTE */
sfr TH4 = 0xF5; /* TIMER 4 DATA - HIGH
BYTE */
sfr EIP1 = 0xF6; /* EXTERNAL INTERRUPT
PRIORITY REGISTER 1 */
sfr EIP2 = 0xF7; /* EXTERNAL INTERRUPT
PRIORITY REGISTER 2 */
sfr SPI0CN = 0xF8; /* SERIAL PERIPHERAL
INTERFACE 0 CONTROL */
sfr PCA0H = 0xF9; /* PCA 0 TIMER - HIGH
BYTE */
sfr PCA0CPH0 = 0xFA; /* CAPTURE/COMPARE
REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
sfr PCA0CPH1 = 0xFB; /* CAPTURE/COMPARE
REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
sfr PCA0CPH2 = 0xFC; /* CAPTURE/COMPARE
REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
sfr PCA0CPH3 = 0xFD; /* CAPTURE/COMPARE
REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
sfr PCA0CPH4 = 0xFE; /* CAPTURE/COMPARE
REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
sfr WDTCN = 0xFF; /* WATCHDOG TIMER
CONTROL */
//-----------------------------------------------------
-------------------------
//-- C8051F020 MCU BIT Addressable
//-----------------------------------------------------
-------------------------
/* TCON 0x88 */
#define __TCON 0x88
sbit TF1 = __TCON ^ 7; /* TIMER 1
OVERFLOW FLAG */
sbit TR1 = __TCON ^ 6; /* TIMER 1 ON/OFF
CONTROL */
sbit TF0 = __TCON ^ 5; /* TIMER 0
OVERFLOW FLAG */
sbit TR0 = __TCON ^ 4; /* TIMER 0 ON/OFF
CONTROL */
sbit IE1 = __TCON ^ 3; /* EXT. INTERRUPT 1
EDGE FLAG */
sbit IT1 = __TCON ^ 2; /* EXT. INTERRUPT 1
TYPE */
sbit IE0 = __TCON ^ 1; /* EXT. INTERRUPT 0
EDGE FLAG */
sbit IT0 = __TCON ^ 0; /* EXT. INTERRUPT 0
TYPE */
/* SCON0 0x98 */
#define __SCON0 0x98
sbit SM00 = __SCON0 ^ 7; /* SERIAL MODE
CONTROL BIT 0 */
sbit SM10 = __SCON0 ^ 6; /* SERIAL MODE
CONTROL BIT 1 */
sbit SM20 = __SCON0 ^ 5; /*
MULTIPROCESSOR COMMUNICATION ENABLE */
sbit REN0 = __SCON0 ^ 4; /* RECEIVE
ENABLE */
sbit TB80 = __SCON0 ^ 3; /* TRANSMIT BIT
8 */
sbit RB80 = __SCON0 ^ 2; /* RECEIVE BIT
8 */
sbit TI0 = __SCON0 ^ 1; /* TRANSMIT
INTERRUPT FLAG */
sbit RI0 = __SCON0 ^ 0; /* RECEIVE
INTERRUPT FLAG */
/* IE 0xA8 */
#define __IE 0xA8
sbit EA = __IE ^ 7; /* GLOBAL INTERRUPT
ENABLE */
sbit ET2 = __IE ^ 5; /* TIMER 2 INTERRUPT
ENABLE */
sbit ES0 = __IE ^ 4; /* UART0 INTERRUPT
ENABLE */
sbit ET1 = __IE ^ 3; /* TIMER 1 INTERRUPT
ENABLE */
sbit EX1 = __IE ^ 2; /* EXTERNAL
INTERRUPT 1 ENABLE */
sbit ET0 = __IE ^ 1; /* TIMER 0 INTERRUPT
ENABLE */
sbit EX0 = __IE ^ 0; /* EXTERNAL
INTERRUPT 0 ENABLE */
/* IP 0xB8 */
#define __IP 0xB8
sbit PT2 = __IP ^ 5; /* TIMER 2 PRIORITY
*/
sbit PS = __IP ^ 4; /* SERIAL PORT
PRIORITY */
sbit PT1 = __IP ^ 3; /* TIMER 1 PRIORITY
*/
sbit PX1 = __IP ^ 2; /* EXTERNAL
INTERRUPT 1 PRIORITY */
sbit PT0 = __IP ^ 1; /* TIMER 0 PRIORITY
*/
sbit PX0 = __IP ^ 0; /* EXTERNAL
INTERRUPT 0 PRIORITY */
/* SMB0CN 0xC0 */
#define __SMB0CN 0xC0
//sbit BUSY = __SMB0CN ^ 7; /* SMBUS 0
BUSY */
//sbit ENSMB = __SMB0CN ^ 6; /* SMBUS 0
ENABLE */
//sbit STA = __SMB0CN ^ 5; /* SMBUS 0
START FLAG */
//sbit STO = __SMB0CN ^ 4; /* SMBUS 0
STOP FLAG */
//sbit SI = __SMB0CN ^ 3; /* SMBUS 0
INTERRUPT PENDING FLAG */
//sbit AA = __SMB0CN ^ 2; /* SMBUS 0
ASSERT/ACKNOWLEDGE FLAG */
//sbit SMBFTE = __SMB0CN ^ 1; /* SMBUS 0
FREE TIMER ENABLE */
//sbit SMBTOE = __SMB0CN ^ 0; /* SMBUS 0
TIMEOUT ENABLE */
sbit BUS_BUSY = __SMB0CN ^ 7;
// SM Bus Busy (bit 7)
sbit BUS_EN = __SMB0CN ^ 6;
// SM Bus Enable (bit 6)
sbit BUS_START = __SMB0CN ^ 5;
// SM Bus Start (bit 5)
sbit BUS_STOP = __SMB0CN ^ 4;
// SM Bus Stop (bit 4)
sbit BUS_INT = __SMB0CN ^ 3;
// SM Bus Interrupt (bit 3)
sbit BUS_AA = __SMB0CN ^ 2;
// SM Bus ACK (bit 2)
sbit BUS_FTE = __SMB0CN ^ 1;
// SM Bus Clock timeout - high (bit 1)
sbit BUS_TOE = __SMB0CN ^ 0;
// SM Bus Clock timeout - low (bit 0)
/* T2CON 0xC8 */
#define __T2CON 0xC8
sbit TF2 = __T2CON ^ 7; /* TIMER 2
OVERFLOW FLAG */
sbit EXF2 = __T2CON ^ 6; /* EXTERNAL
FLAG */
sbit RCLK = __T2CON ^ 5; /* RECEIVE CLOCK
FLAG */
sbit TCLK = __T2CON ^ 4; /* TRANSMIT
CLOCK FLAG */
sbit EXEN2 = __T2CON ^ 3; /* TIMER 2
EXTERNAL ENABLE FLAG */
sbit TR2 = __T2CON ^ 2; /* TIMER 2 ON/OFF
CONTROL */
sbit CT2 = __T2CON ^ 1; /* TIMER OR
COUNTER SELECT */
sbit CPRL2 = __T2CON ^ 0; /* CAPTURE OR
RELOAD SELECT */
/* PSW 0xD0 */
#define __PSW 0xD0
sbit CY = __PSW ^ 7; /* CARRY
FLAG */
sbit AC = __PSW ^ 6; /* AUXILIARY CARRY
FLAG */
sbit F0 = __PSW ^ 5; /* USER FLAG
0 */
sbit RS1 = __PSW ^ 4; /* REGISTER BANK
SELECT 1 */
sbit RS0 = __PSW ^ 3; /* REGISTER BANK
SELECT 0 */
sbit OV = __PSW ^ 2; /* OVERFLOW
FLAG */
sbit F1 = __PSW ^ 1; /* USER FLAG
1 */
sbit P = __PSW ^ 0; /* ACCUMULATOR
PARITY FLAG */
/* PCA0CN D8H */
#define __PCA0CN 0xD8
sbit CF = __PCA0CN ^ 7; /* PCA 0 COUNTER
OVERFLOW FLAG */
sbit CR = __PCA0CN ^ 6; /* PCA 0 COUNTER
RUN CONTROL BIT */
sbit CCF4 = __PCA0CN ^ 4; /* PCA 0 MODULE
4 INTERRUPT FLAG */
sbit CCF3 = __PCA0CN ^ 3; /* PCA 0 MODULE
3 INTERRUPT FLAG */
sbit CCF2 = __PCA0CN ^ 2; /* PCA 0 MODULE
2 INTERRUPT FLAG */
sbit CCF1 = __PCA0CN ^ 1; /* PCA 0 MODULE
1 INTERRUPT FLAG */
sbit CCF0 = __PCA0CN ^ 0; /* PCA 0 MODULE
0 INTERRUPT FLAG */
/* ADC0CN 0xE8 */
#define __ADC0CN 0xE8
sbit AD0EN = __ADC0CN ^ 7; /* ADC 0
ENABLE */
sbit AD0TM = __ADC0CN ^ 6; /* ADC 0 TRACK
MODE */
sbit AD0INT = __ADC0CN ^ 5; /* ADC 0
CONVERISION COMPLETE INTERRUPT FLAG */
sbit AD0BUSY = __ADC0CN ^ 4; /* ADC 0 BUSY
FLAG */
sbit AD0CM1 = __ADC0CN ^ 3; /* ADC 0 START
OF CONVERSION MODE BIT 1 */
sbit AD0CM0 = __ADC0CN ^ 2; /* ADC 0 START
OF CONVERSION MODE BIT 0 */
sbit AD0WINT = __ADC0CN ^ 1; /* ADC 0
WINDOW COMPARE INTERRUPT FLAG */
sbit AD0LJST = __ADC0CN ^ 0; /* ADC 0 RIGHT
JUSTIFY DATA BIT */
/* SPI0CN 0xF8 */
#define __SPI0CN 0xF8
sbit SPIF = __SPI0CN ^ 7; /* SPI 0 INTERRUPT
FLAG */
sbit WCOL = __SPI0CN ^ 6; /* SPI 0 WRITE
COLLISION FLAG */
sbit MODF = __SPI0CN ^ 5; /* SPI 0 MODE
FAULT FLAG */
sbit RXOVRN = __SPI0CN ^ 4; /* SPI 0 RX
OVERRUN FLAG */
sbit TXBSY = __SPI0CN ^ 3; /* SPI 0 TX BUSY
FLAG */
sbit SLVSEL = __SPI0CN ^ 2; /* SPI 0 SLAVE
SELECT */
sbit MSTEN = __SPI0CN ^ 1; /* SPI 0 MASTER
ENABLE */
sbit SPIEN = __SPI0CN ^ 0; /* SPI 0 SPI ENABLE
*/
//-----------------------------------------------------
------------------------
// Not BIT ADDRESSABLE REGISTERS
//-----------------------------------------------------
------------------------
//-- SCON1 = 0xF1
#define SM01_BIT (0x1<<7) /* SERIAL MODE
CONTROL BIT 0 */
#define SM11_BIT (0x1<<6) /* SERIAL MODE
CONTROL BIT 1 */
#define SM21_BIT (0x1<<5) /* MULTIPROCESSOR
COMMUNICATION ENABLE */
#define REN1_BIT (0x1<<4) /* RECEIVE
ENABLE */
#define TB81_BIT (0x1<<3) /* TRANSMIT BIT
8 */
#define RB81_BIT (0x1<<2) /* RECEIVE BIT
8 */
#define TI1_BIT (0x1<<1) /* TRANSMIT INTERRUPT
FLAG */
#define RI1_BIT (0x1<<0) /* RECEIVE INTERRUPT
FLAG */
//-- PCA0CPMn n=0..4
#define PCA_PWM16 (0x1<<7)
#define PCA_ECOM (0x1<<6)
#define PCA_CAPP (0x1<<5)
#define PCA_CAPN (0x1<<4)
#define PCA_MAT (0x1<<3)
#define PCA_TOG (0x1<<2)
#define PCA_PWM (0x1<<1)
#define PCA_EECF (0x1<<0)
#endif
-----------------------------------------------------
In order to compile my project i developed a .bat file
(as was suggested reading the forum)... basically this
file is the follow:
-----------------------------------------------------
SET PATH=C:\PROJECTS\C51
\prokin\prokin_fw_sdcc\;C:\SDCC\BIN
CD C:\PROJECTS\C51\prokin\prokin_fw_sdcc\
SDCC --version
del *.rel
del *.ihx
del *.map
del *.mem
SDCC -mmcs51 -c --debug --model-large -I../../include
putchar.c
SDCC -mmcs51 -c --debug --model-large -I../../include
_getkey.c
SDCC -mmcs51 -c --debug --model-large -I../../include
startup.c
SDCC -mmcs51 -c --debug --model-large -I../../include
main.c
SDCC -mmcs51 -c --debug --model-large -I../../include
acc_pwm.c
SDCC -mmcs51 --model-large --debug --idata-loc
0x20 --iram-size 256 --xram-loc 0x0 --xram-size
0x0FFF -code-loc 0x0 --code-size 0xFDFF main.rel
startup.rel putchar.rel _getkey.rel acc_pwm.rel
packihx main.ihx > firmware.hex
------------------------------------------------------
If you want the project source code (a .zip file) ,I can
send.
I'm actually triing using a more sample project (HELLO
WORLD). In order to understand my problem.
Can someone help me?
Logged In: YES
user_id=888171
New C8051F020.h solved the problem.