From: SourceForge.net <no...@so...> - 2004-09-21 20:48:23
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Patches item #1032155, was opened at 2004-09-21 20:48 Message generated for change (Tracker Item Submitted) made by Item Submitter You can respond by visiting: https://sourceforge.net/tracker/?func=detail&atid=300599&aid=1032155&group_id=599 Category: None Group: None Status: Open Resolution: None Priority: 5 Submitted By: ccsporters (tecodev) Assigned to: Nobody/Anonymous (nobody) Summary: Fix for shiftL2Left2Result Initial Comment: While reading the codegeneration functions in the PIC16 port for various shift operations, I found one bug and a few minor inefficiencies. gen.c:8084 had a wrong literal 0xF0 instead of 0x0F This would create wrong results for i << 5 with an int i. gen.c:8218 reads the sign bit after some rotations from the wrong place. Bit 15 from the left operand is only once rotated into result+offr<bit 0> This would cause "i >> 6" to fail for signed ints i, but the compiler does not erach this point (see my bugreport #1032131). Minor improvements are: gen.c:7728ff one instruction can be saved by replacing two RLCFW by one RLNCWF as the carry bit is ignored afterwards gen.c:7744ff (same thing) gen.c:7858ff one instruction can be saved by not clearing the carry bit explicitly but replacing RRCF by RRNCF and clearing bit 0 in the AND instruction above Later (in case 6:) another instruction can be saved by replacing RLCF with RLNCF and thus keeping the carry bit in the register (also have to modify the AND mask above) gen.c:8354ff shiftLLong The if-statements (size >= something) allowed for access beyond the size of the result operand (via the MOVWF instructions with MSBxx+offr) --- though these cases would only occur for queer result sizes (e.g. 3). Patch to be applied in src/pic16 with -p0. BTW: These routines have certainly been a good deal of work, thank you for your engagement! Raphael Neider ---------------------------------------------------------------------- You can respond by visiting: https://sourceforge.net/tracker/?func=detail&atid=300599&aid=1032155&group_id=599 |
From: SourceForge.net <no...@so...> - 2004-09-24 07:57:31
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Patches item #1032155, was opened at 2004-09-21 23:48 Message generated for change (Comment added) made by vrokas You can respond by visiting: https://sourceforge.net/tracker/?func=detail&atid=300599&aid=1032155&group_id=599 Category: None Group: None >Status: Pending >Resolution: Accepted Priority: 5 Submitted By: ccsporters (tecodev) >Assigned to: Vangelis Rokas (vrokas) Summary: Fix for shiftL2Left2Result Initial Comment: While reading the codegeneration functions in the PIC16 port for various shift operations, I found one bug and a few minor inefficiencies. gen.c:8084 had a wrong literal 0xF0 instead of 0x0F This would create wrong results for i << 5 with an int i. gen.c:8218 reads the sign bit after some rotations from the wrong place. Bit 15 from the left operand is only once rotated into result+offr<bit 0> This would cause "i >> 6" to fail for signed ints i, but the compiler does not erach this point (see my bugreport #1032131). Minor improvements are: gen.c:7728ff one instruction can be saved by replacing two RLCFW by one RLNCWF as the carry bit is ignored afterwards gen.c:7744ff (same thing) gen.c:7858ff one instruction can be saved by not clearing the carry bit explicitly but replacing RRCF by RRNCF and clearing bit 0 in the AND instruction above Later (in case 6:) another instruction can be saved by replacing RLCF with RLNCF and thus keeping the carry bit in the register (also have to modify the AND mask above) gen.c:8354ff shiftLLong The if-statements (size >= something) allowed for access beyond the size of the result operand (via the MOVWF instructions with MSBxx+offr) --- though these cases would only occur for queer result sizes (e.g. 3). Patch to be applied in src/pic16 with -p0. BTW: These routines have certainly been a good deal of work, thank you for your engagement! Raphael Neider ---------------------------------------------------------------------- >Comment By: Vangelis Rokas (vrokas) Date: 2004-09-24 10:57 Message: Logged In: YES user_id=770505 Please upload again the patch file adding options -cp when running diff ---------------------------------------------------------------------- You can respond by visiting: https://sourceforge.net/tracker/?func=detail&atid=300599&aid=1032155&group_id=599 |
From: SourceForge.net <no...@so...> - 2004-09-24 09:23:48
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Patches item #1032155, was opened at 2004-09-21 20:48 Message generated for change (Comment added) made by tecodev You can respond by visiting: https://sourceforge.net/tracker/?func=detail&atid=300599&aid=1032155&group_id=599 Category: None Group: None >Status: Open Resolution: Accepted Priority: 5 Submitted By: ccsporters (tecodev) Assigned to: Vangelis Rokas (vrokas) Summary: Fix for shiftL2Left2Result Initial Comment: While reading the codegeneration functions in the PIC16 port for various shift operations, I found one bug and a few minor inefficiencies. gen.c:8084 had a wrong literal 0xF0 instead of 0x0F This would create wrong results for i << 5 with an int i. gen.c:8218 reads the sign bit after some rotations from the wrong place. Bit 15 from the left operand is only once rotated into result+offr<bit 0> This would cause "i >> 6" to fail for signed ints i, but the compiler does not erach this point (see my bugreport #1032131). Minor improvements are: gen.c:7728ff one instruction can be saved by replacing two RLCFW by one RLNCWF as the carry bit is ignored afterwards gen.c:7744ff (same thing) gen.c:7858ff one instruction can be saved by not clearing the carry bit explicitly but replacing RRCF by RRNCF and clearing bit 0 in the AND instruction above Later (in case 6:) another instruction can be saved by replacing RLCF with RLNCF and thus keeping the carry bit in the register (also have to modify the AND mask above) gen.c:8354ff shiftLLong The if-statements (size >= something) allowed for access beyond the size of the result operand (via the MOVWF instructions with MSBxx+offr) --- though these cases would only occur for queer result sizes (e.g. 3). Patch to be applied in src/pic16 with -p0. BTW: These routines have certainly been a good deal of work, thank you for your engagement! Raphael Neider ---------------------------------------------------------------------- >Comment By: ccsporters (tecodev) Date: 2004-09-24 09:23 Message: Logged In: YES user_id=1115835 I just uploaded the new version of the patch. Raphael ---------------------------------------------------------------------- Comment By: Vangelis Rokas (vrokas) Date: 2004-09-24 07:57 Message: Logged In: YES user_id=770505 Please upload again the patch file adding options -cp when running diff ---------------------------------------------------------------------- You can respond by visiting: https://sourceforge.net/tracker/?func=detail&atid=300599&aid=1032155&group_id=599 |
From: SourceForge.net <no...@so...> - 2004-10-01 18:44:56
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Patches item #1032155, was opened at 2004-09-21 23:48 Message generated for change (Comment added) made by vrokas You can respond by visiting: https://sourceforge.net/tracker/?func=detail&atid=300599&aid=1032155&group_id=599 Category: None Group: None >Status: Closed Resolution: Accepted Priority: 5 Submitted By: ccsporters (tecodev) Assigned to: Vangelis Rokas (vrokas) Summary: Fix for shiftL2Left2Result Initial Comment: While reading the codegeneration functions in the PIC16 port for various shift operations, I found one bug and a few minor inefficiencies. gen.c:8084 had a wrong literal 0xF0 instead of 0x0F This would create wrong results for i << 5 with an int i. gen.c:8218 reads the sign bit after some rotations from the wrong place. Bit 15 from the left operand is only once rotated into result+offr<bit 0> This would cause "i >> 6" to fail for signed ints i, but the compiler does not erach this point (see my bugreport #1032131). Minor improvements are: gen.c:7728ff one instruction can be saved by replacing two RLCFW by one RLNCWF as the carry bit is ignored afterwards gen.c:7744ff (same thing) gen.c:7858ff one instruction can be saved by not clearing the carry bit explicitly but replacing RRCF by RRNCF and clearing bit 0 in the AND instruction above Later (in case 6:) another instruction can be saved by replacing RLCF with RLNCF and thus keeping the carry bit in the register (also have to modify the AND mask above) gen.c:8354ff shiftLLong The if-statements (size >= something) allowed for access beyond the size of the result operand (via the MOVWF instructions with MSBxx+offr) --- though these cases would only occur for queer result sizes (e.g. 3). Patch to be applied in src/pic16 with -p0. BTW: These routines have certainly been a good deal of work, thank you for your engagement! Raphael Neider ---------------------------------------------------------------------- >Comment By: Vangelis Rokas (vrokas) Date: 2004-10-01 21:44 Message: Logged In: YES user_id=770505 Patch applied successfully. SDCC version 2.4.5 #851 ---------------------------------------------------------------------- Comment By: ccsporters (tecodev) Date: 2004-09-24 12:23 Message: Logged In: YES user_id=1115835 I just uploaded the new version of the patch. Raphael ---------------------------------------------------------------------- Comment By: Vangelis Rokas (vrokas) Date: 2004-09-24 10:57 Message: Logged In: YES user_id=770505 Please upload again the patch file adding options -cp when running diff ---------------------------------------------------------------------- You can respond by visiting: https://sourceforge.net/tracker/?func=detail&atid=300599&aid=1032155&group_id=599 |