Hello,

I have a question regarding a Makefile that holds multiple targets and has to compile specific code using a compile time define.

For example the following Makefile:

libs = file1.rel file2.rel file3.rel
srcs = $(libs,.rel=.c)

%.rel : %.c
$(CC) $(CFLAGS) -c $<

all: target1.hex
target2: target2.hex
target3: target3.hex

target1.hex: application.c $(libs)
      sdcc $(CFLAGS) $(LFLAGS) application.c $(libs) -DTARGET1
      packihx <application.ihx >bins/application.hex

target2.hex: application.c $(libs)
      sdcc $(CFLAGS) $(LFLAGS) application.c $(libs) -DTARGET2
      packihx <application.ihx >bins/application.hex

target3.hex: application.c $(libs)
      sdcc $(CFLAGS) $(LFLAGS) application.c $(libs) -DTARGET3
      packihx <application.ihx >bins/application.hex


If I understand correct, before application.c is compiled for a target, the libs are already compiled. But actually I want that the define is also passed at compile time to the lib files (file1,file2 and file3).
Can anyone point me to an example of a Makefile for SDCC with such a construction or a hint on how this can be solved?

Regards,
Gerard