The aim is to predict the execution time of given program. But, since there is given the number of cycles for each instruction surely there is no pipeline since otherwise the cycle count for given instruction would depend on previous instruction(s).


Date: Wed, 22 May 2013 15:04:22 -0400
Subject: Re: [sdcc-devel] Instruction pipeline

On 5/22/2013 8:02 AM, Kujtim Hyseni wrote:

I couldn't contact atmel so I directed the question to you: Do 8051 microcontroller's CPU apply instruction pipeline during code execution. More precisely the 8051 microcontroller of type AT89S8253?




Just curious, but what is your objective in determining if that particular microcontroller has
instruction pipelining ?  I have not heard of a superscalar pipeline for the 8051 (one
where multiple instructions would be in the pipeline at the same time).  For the atmel
chips that reduce the basic cycle count down to 4 (a nop takes 4 cycles), almost
all the instructions take some multiple of 4 cycles.  Instructions like movx would
take either 8 or 12 cycles; which you should be able to find in the instruction reference.


------------------------------------------------------------------------------ Try New Relic Now & We'll Send You this Cool Shirt New Relic is the only SaaS-based application performance monitoring service that delivers powerful full stack analytics. Optimize and monitor your browser, app, & servers with just a few lines of code. Try New Relic and get this awesome Nerd Life shirt!
_______________________________________________ sdcc-devel mailing list