Ralph,

Thanks very much.  You were right, the .rel files were just preprocessed source code (which I noticed before and was confused about).  I'm using sdcc to compile now, and after some tweaking of flags and changing stuff that the Keil compiler didn't care about but sdcc does, all my code compiles now, and I'm on to real linker errors.

I am doing a link like so:
sdcc --stack-size 64 --model-small --xram-loc 0x0000 --xram-size 0x1000 --iram-size 0x0100 --code-loc 0x0000 --code-size 0xFBFF main.rel can.rel ADC.rel Uart0.rel Timers.rel Clock.rel PortConfig.rel

and I get the errors:
memory overlap at 0x0 for RSEG0
memory overlap at 0x1 for RSEG0
memory overlap at 0x0 for RSEG0
memory overlap at 0x1 for RSEG0

I don't quite understand the syntax of the error message.  Is it saying that there's a segment named RSEG0 that is full?  I searched all my code and all the generated files for RSEG0, and the only place it occurs is in the "Area Table" in all the generated .sym files, and in the the generated .rel files.  Unfortunately I don't know how to interpret either, or what RSEG and RSEG0/RSEG1 mean.

Here's what's in my .sym files:
ADC.sym:1278:   2 RSEG0                                                                              size    2   flags 8
can.sym:2576:   2 RSEG0                                                                              size    2   flags 8
Clock.sym:1190:   2 RSEG0                                                                              size    0   flags 8
main.sym:2289:   2 RSEG0                                                                              size    0   flags 8
PortConfig.sym:1202:   2 RSEG0                                                                              size    0   flags 8
Timers.sym:1242:   2 RSEG0                                                                              size    4   flags 8
Uart0.sym:2256:   2 RSEG0                                                                              size    0   flags 8

and here's what's in my .rel files:
ADC.rel:835:A RSEG0 size 2 flags 8 addr 0
can.rel:837:A RSEG0 size 2 flags 8 addr 0
Clock.rel:822:A RSEG0 size 0 flags 8 addr 0
main.rel:860:A RSEG0 size 0 flags 8 addr 0
PortConfig.rel:822:A RSEG0 size 0 flags 8 addr 0
Timers.rel:834:A RSEG0 size 4 flags 8 addr 0
Uart0.rel:836:A RSEG0 size 0 flags 8 addr 0

Any docs that could help me out?  I can reply with the full .rel and .sym files, or source code or pre-processed source code, if it would help.

Thanks,
Miles

On Thu, Sep 3, 2009 at 5:30 PM, Raphael Neider <rneider@web.de> wrote:
Hi Miles,

> PS: Not sure if it's related, but I compiled my code with sdcpp, instead
> of sdcc.  I can't figure out how to give an -MD option to sdcc so that it
> passes it on to sdcpp, so I just called sdcpp directly (even though I've
> often found it to be problematic to call g++ directly, instead of letting
> gcc do it.  Does sdcc work the same way?).  Here's how I invoked the
> compiler:
>
> sdcpp can.c -debug -Ic:/full/path/to/sdcc/include -MD main.d -o main.rel

sdcpp is SDCC's adaptation of GCC's C preprocessor cpp -- it is not a C++
compiler. The output main.rel is probably plain C -- with all macros
expanded.

If you want to pass specific options on to the preprocessor, use

sdcc -Wp,-debug,-MD,main.d -Ic:/full/path/to/sdcc/include -o main.rel can.c

(assuming you want the default target, some 8051; otherwise you would have
to include -m z80 or -m pic -p16f877 or ... Same mechanism works for
assembler
(-Wa,-opt,-opt,arg,arg) and linker (-Wl,-opt,-opt,-opt,arg,-opt).

Hope that gets you started,
Raphael

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