#931 MOS6502, MOS65C02 - interrupt implementation

[Andrzej]

The question is simple: How to implement the NMI and IRQ interrupt routines in MOC6502 or MOC65C02?

It is possible with default crt0.rel, or must I modify crt0.s and compile own crt0.rel?

If there info is documented, where is this? I did not found this information in SDCC manual.

I suppose, that raising the interrupt at the software perspective is very simple: Push flag register and program counter on the stack and change the PC to the value stored at the two bytes 0xFFFA,0xFFFB or 0xFFFE,0xFFFF for the NMI or IRQ respectively.

I tried to implement these routines like Z180 (with modified crt0.rel) and MSC51:

void NMI_InterruptHandler(void) __critical __interrupt 
{
}

void IM1_InterruptHandler(void) __interrupt
{
}

void irq_int(void) __interrupt (1)
{
}

But none of the routine is not invoked if I force interrupt raise, and at the mentioned interrupt addresses are the same value like at the 0xFFFC,0xFFFD, the program entry point. So, raising the NMI or IRQ causes the program reset.

[Maarten Brock]

https://sourceforge.net/p/sdcc/code/HEAD/tree/trunk/sdcc/device/lib/mos6502/crt0.s

shows that all vectors point to the same point. So you will have to create your own.

[Andrzej]

Thank you, the modification of original crt0 and compiling using sdas6500 helps me.

The next question is about memory organization. Is this possible to compile MOS6502/MOS65C02 code for use separated Code ROM and Data RAM, like a MCS51? I do not have any physical device with 65C02, but I am using the SDCC for simulations. It is possible, that 6502 has two memories. The first is ROM and occupies almost whole space in exception of first 512 bytes (to work zero-page and stack) and may contain about 60kB of program code and constants, the second memory has also 64kB and is the RAM memory, where are working data. Such double-memory organization is possible in MCS51 and the second RAM memory is called XRAM and SDCC uses them seamlessly.

[Maarten Brock]

For the mcs51 this is native. It has separate instructions to read from code memory (movc) or external memory (movx) and also separate chip selects for external ROM and external RAM. I don't believe the 6502 has any such provisions. So the only option left is bank switching which is much harder and less efficient. I think the short answer is no.