I am using sdcc for gbz80. Had a look at the generated assembly and was surprised to see this code:
Why is not simply this generated?
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The optimization should be done in the peephole optimizer. Currently there are nearly no peephole rules enabled for gbz80. Someone should go through all z80 peephole rules and add those that would work on the gbz80 to the gbz80 rules.
Since the peephole optimizer is a time expensive part of the compilation it would be advantageous to try to put this optimization in the code generator.
With the new register allocation this situation changes drastically:
1) The register allocator needs a lot of time
2) The code is much better already after code generation, thus we can remove many existing peephole rules
The reason current code genration goes through hl is this:
We might need the same value in hl later on, thus it might be better to put it into hl, just in case: The peephole optimizer can optimize it out if not.
In the long run IMO, this should be solved using rematerializeable variables, allowing the register allocator to make this decision. The new allocator is expensive in terms of run time, but it gives optimality.
P.S.: This comment applies top both the z80 and gbz80 ports.
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