PIC 18F458 CAN BUS & Active bank

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Richard G
2005-06-28
2013-03-12
  • Richard G

    Richard G - 2005-06-28

    Hello, I'm developing CAN bus devices.

    I am having a problem with the 'active bank' not being used for registers F7Fh through F60h.

    it should be used for F60h through FFFh but only the higher 128 bytes of this subset of bank 15 are being accessed in the correct way
    (i gpdasm'ed the hex to discover this (using a simple file with arbitrary read/write to the sfr's in question))

    please can someone tell me where i can specify to sdcc that these addresses are in the active bank and use a=0 in instructions that access them.

    my .lkr script is setup correctly as far as i can see, with the ACTIVEBANK accesssfr in the correct place.

    sdcc uses the active bank for other sfr access, what am i doing wrong?

    thanks in advance

    Richard

    (here is my lkr script)

    LIBPATH .

    FILES crt0iz.o
    FILES libc18f.lib
    FILES libsdcc.lib

    FILES pic18f458.lib
    FILES libio18f458.lib
    FILES libm18f.lib
    FILES gptrget1.o

    CODEPAGE   NAME=vectors    START=0x0            END=0x29           PROTECTED
    CODEPAGE   NAME=page       START=0x2A           END=0x7FFF
    CODEPAGE   NAME=idlocs     START=0x200000       END=0x200007       PROTECTED
    CODEPAGE   NAME=config     START=0x300000       END=0x30000D       PROTECTED
    CODEPAGE   NAME=devid      START=0x3FFFFE       END=0x3FFFFF       PROTECTED
    CODEPAGE   NAME=eedata     START=0xF00000       END=0xF000FF       PROTECTED

    ACCESSBANK NAME=accessram  START=0x0            END=0x5F
    DATABANK   NAME=gpr0       START=0x60           END=0xFF
    DATABANK   NAME=gpr1       START=0x100          END=0x1FF
    DATABANK   NAME=gpr2       START=0x200          END=0x2FF
    DATABANK   NAME=gpr3       START=0x300          END=0x3FF
    DATABANK   NAME=largebank  START=0x400          END=0x5FF

    DATABANK   NAME=bankedsfr  START=0xF00          END=0xF5F          PROTECTED
    ACCESSBANK NAME=accesssfr  START=0xF60          END=0xFFF          PROTECTED

    SECTION    NAME=CONFIG     ROM=config

    STACK SIZE=0x100 RAM=gpr3

     
    • Richard G

      Richard G - 2005-07-01

      OK I have found a solution, it may be a bug...

      around line 940 of ralloc.c in the sdcc/src/pic16 directory there exists some workaround code... the values used in the code were the same as those for a 18f452, by changing them to those of a 18f458 i found the access bank was used correctly when accessing my CAN registers (window controlled ones).

      the original code was:
              if((reg->address>= 0x00 && reg->address < 0x80)
                  || (reg->address >= 0xf80 && reg->address <= 0xfff))
                  reg->accessBank = 1;

      i have changed this (for my own purposes) to:
              if((reg->address>= 0x00 && reg->address < 0x60)
              || (reg->address >= 0xf60 && reg->address <= 0xfff))
              reg->accessBank = 1;

      A hard coded range of memory locations seems a bad idea for a multi device port of a compiler.... I noticed there are parameters such as "active bank off set" in the device.c file, maybe someone could adapt this workaround to use such values (or remove the need for a workaround all together).
      suggestion:
              if((reg->address>= 0x00 && reg->address < "<<access bank offset variable>>")
              || (reg->address >= "<<access bank offset variable>>" && reg->address <= 0xfff))
              reg->accessBank = 1;

      I hope someone more familiar with the internals of the compiler takes a look at this, sdcc has great potential and I look forward to a future working with it.

      Richard

       
    • Raphael Neider

      Raphael Neider - 2005-09-05

      This indeed is a bug and should have been posted as such in the tracker system. Then I would have realized and fixed it earlier... Anyway, thanks for the report.
      This issue is now (SDCC 2.5.3 #1106+) fixed.

       

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