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AT89LP support

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Vasi
2016-04-27
2016-04-27
  • Vasi

    Vasi - 2016-04-27

    Hi,

    I would like to know why we don't have support for AT89LP51RD2-ED2-ID2 microcontrollers from Atmel/Microchip? I know that these are supported in a 2.9.0 version of SDCC provided by Atmel.

     
  • Maarten Brock

    Maarten Brock - 2016-04-27

    What is the difference between the AT89LP51ED2 and the AT89C51ED2? Would that require a new header file? Or what kind of support are you looking for?

     
  • Philipp Klaus Krause

    Isn't that just an 8051 clone, and thus should be supported by SDCC? Does Atmel's 2.9.0 version use the instruction set extensions, i.e. MAC and second data pointer?

    Philipp

     
  • Cristiano Rodrigues

    Hi there :)
    It's not just a clone. It's a faster one and with 12 new instructions.
    The MAC instruction seems to be interesting and I think that atmel's sdcc is not using it.
    for that code:

    #include ".\teste.h"
    #include <AT89LP51RD2.h>
    #include <stdlib.h>
    #include <stdint.h>
    
    // Uncomment line below to skip static & global variable initialization
    // int _sdcc_external_startup() { return 1;}
    
    void main(void)
    {
        uint16_t aaa, bbb, ccc;
    
        aaa = 0x11;
        bbb = 0x22;
    
        ccc = aaa * bbb;
    
        while(1)
        {
            ;
        }
    
    }
    

    I get that disassembly:

    0000: 02 00 08          LJMP  0x0008     
    0003: 12 00 64          LCALL ??0009     
    0006: 80 fe             SJMP  0x0006    
    0008: 75 81 07          MOV   SP, #0x07
    000b: 12 00 66          LCALL ??000a     
    000e: e5 82             MOV   A, DPL
    0010: 60 03             JZ    ??0000    
    0012: 02 00 03          LJMP  0x0003     
    0015: 79 00     ??0000: MOV   R1, #0x00
    0017: e9                MOV   A, R1  
    0018: 44 00             ORL   A, #0x00
    001a: 60 1b             JZ    ??0003    
    001c: 7a 00             MOV   R2, #0x00
    001e: 90 00 6a          MOV   DPTR, #0x006A
    0021: 78 00             MOV   R0, #0x00
    0023: 75 a0 00          MOV   P2, #0x00
    0026: e4        ??0001: CLR   A      
    0027: 93                MOVC  A, @A+DPTR
    0028: f2                MOVX  @R0, A 
    0029: a3                INC   DPTR    
    002a: 08                INC   R0     
    002b: b8 00 02          CJNE  R0, #0x00, ??0002 
    002e: 05 a0             INC   P2   
    0030: d9 f4     ??0002: DJNZ  R1, ??0001 
    0032: da f2             DJNZ  R2, ??0001 
    0034: 75 a0 ff          MOV   P2, #0xFF
    0037: e4        ??0003: CLR   A      
    0038: 78 ff             MOV   R0, #0xFF
    003a: f6        ??0004: MOV   @R0, A 
    003b: d8 fd             DJNZ  R0, ??0004 
    003d: 78 00             MOV   R0, #0x00
    003f: e8                MOV   A, R0  
    0040: 44 00             ORL   A, #0x00
    0042: 60 0a             JZ    ??0006    
    0044: 79 00             MOV   R1, #0x00
    0046: 75 a0 00          MOV   P2, #0x00
    0049: e4                CLR   A      
    004a: f3        ??0005: MOVX  @R1, A 
    004b: 09                INC   R1     
    004c: d8 fc             DJNZ  R0, ??0005 
    004e: 78 00     ??0006: MOV   R0, #0x00
    0050: e8                MOV   A, R0  
    0051: 44 00             ORL   A, #0x00
    0053: 60 0c             JZ    ??0008    
    0055: 79 00             MOV   R1, #0x00
    0057: 90 00 00          MOV   DPTR, #0x0000
    005a: e4                CLR   A      
    005b: f0        ??0007: MOVX  @DPTR, A
    005c: a3                INC   DPTR    
    005d: d8 fc             DJNZ  R0, ??0007 
    005f: d9 fa             DJNZ  R1, ??0007 
    0061: 02 00 03  ??0008: LJMP  0x0003     
    0064: 80 fe     ??0009: SJMP  ??0009    
    0066: 75 82 00  ??000a: MOV   DPL, #0x00
    0069: 22                RET          
    

    Do you think that is possible to optimize a little bit the sdcc (mcs51) to the AT89LP?

    AN_3716 - Migrating from AT89C51RB2/RC2/RD2/ED2/IC2/ID2 to AT89LP51RB2/RC2/RD2/ED2/IC2/ID2

     

    Last edit: Cristiano Rodrigues 2017-03-31
  • Frieder Ferlemann

    Hi Christiano,

    within the above disassembly the code generated for your function void main(void) is just

    0064: 80 fe     ??0009: SJMP  ??0009    
    0066: 75 82 00  ??000a: MOV   DPL, #0x00
    0069: 22                RET      
    

    which is probably not what you want. You might want to use "volatile" or do something that causes side effects for the compiler to actually do something.

    (You do not seem to be using a recent version of SDCC)

    Your code cannot be mapped to the AT89LP though. The MAC only operates on signed 16 bit.

    Nothing stops you from using the MAC "by hand" though: loading the variables to the SFR (you can access them 16 bit wise) then issuing the MAC instruction via inline assembly, then reading the output SFR.
    The include file AT89LP51RD2.h is not part of SDCC so it's not clear whether it already contains some MAC support. The include file which might come closest on SDCC's side is probably device/include/mcs51/C8051F120.h (also has a MAC).

     
  • Cristiano Rodrigues

    Hi Frieder!
    Thanks for your response.
    I misread the datasheet and the MAC is indeed for signed 16bit.
    The used SDCC was adapted by ATMEL. I'm using it just to see if they are using some of the 12 new instructions.

    Small Device C Compiler (SDCC) Version 2.9.0 - Source

    here it is the AT89LP51RD2.h made by Atmel

    /*H****************************************************************************
    * NAME: at89lp51rd2.h
    *------------------------------------------------------------------------------
    * PURPOSE:
    *   This file defines Sfr registers and BIT Registers for AT89LP51RD2 on SDCC compiler
    ******************************************************************************/
    #define Sfr(x, y)   __sfr __at (y) x
    #define Sbit(x, y, z)   __sbit __at (y^z) x
    
    /*----------------------------------------*/
    /* Include file for 8051 SFR Definitions  */
    /*----------------------------------------*/
    
    Sfr (P0 , 0x80);
    /* ---  P0 Bits --- */
    Sbit (P0_0 , 0x80, 0);
    Sbit (P0_1 , 0x80, 1);
    Sbit (P0_2 , 0x80, 2);
    Sbit (P0_3 , 0x80, 3);
    Sbit (P0_4 , 0x80, 4);
    Sbit (P0_5 , 0x80, 5);
    Sbit (P0_6 , 0x80, 6);
    Sbit (P0_7 , 0x80, 7);
    
    Sfr (TCON , 0x88);
    /* ---  TCON Bits --- */
    Sbit (TF1 , 0x88, 7);
    Sbit (TR1 , 0x88, 6);
    Sbit (TF0 , 0x88, 5);
    Sbit (TR0 , 0x88, 4);
    Sbit (IE1 , 0x88, 3);
    Sbit (IT1 , 0x88, 2);
    Sbit (IE0 , 0x88, 1);
    Sbit (IT0 , 0x88, 0);
    
    Sfr (P1 , 0x90);
    /* ---  P1 Bits --- */
    Sbit (T2 , 0x90, 0);
    Sbit (T2EX , 0x90, 1);
    Sbit (ECI , 0x90, 2);
    Sbit (CEX0 , 0x90, 3);
    Sbit (CEX1 , 0x90, 4);
    Sbit (CEX2 , 0x90, 5);
    Sbit (CEX3 , 0x90, 6);
    Sbit (CEX4 , 0x90, 7);
    Sbit (SSB , 0x90, 1);
    Sbit (MISO , 0x90, 5);
    Sbit (SCK , 0x90, 6);
    Sbit (MOSI , 0x90, 7);
    /* ---  P1 Bits --- */
    Sbit (P1_0 , 0x90, 0);
    Sbit (P1_1 , 0x90, 1);
    Sbit (P1_2 , 0x90, 2);
    Sbit (P1_3 , 0x90, 3);
    Sbit (P1_4 , 0x90, 4);
    Sbit (P1_5 , 0x90, 5);
    Sbit (P1_6 , 0x90, 6);
    Sbit (P1_7 , 0x90, 7);
    
    Sfr (SCON , 0x98);
    /* --- SCON Bits ---- */
    Sbit (SM0 , 0x98, 7);
    Sbit (SM1 , 0x98, 6);
    Sbit (SM2 , 0x98, 5);
    Sbit (REN , 0x98, 4);
    Sbit (TB8 , 0x98, 3);
    Sbit (RB8 , 0x98, 2);
    Sbit (TI , 0x98, 1);
    Sbit (RI , 0x98, 0);
    
    Sfr (P2 , 0xA0);
    /* ---  P2 Bits --- */
    Sbit (P2_0 , 0xA0, 0);
    Sbit (P2_1 , 0xA0, 1);
    Sbit (P2_2 , 0xA0, 2);
    Sbit (P2_3 , 0xA0, 3);
    Sbit (P2_4 , 0xA0, 4);
    Sbit (P2_5 , 0xA0, 5);
    Sbit (P2_6 , 0xA0, 6);
    Sbit (P2_7 , 0xA0, 7);
    
    Sfr (IEN0 , 0xA8);
    /* --- IEN0 Bits ----- */
    Sbit (EA , 0xA8, 7);
    Sbit (EC , 0xA8, 6);
    Sbit (ET2 , 0xA8, 5);
    Sbit (ES , 0xA8, 4);
    Sbit (ET1 , 0xA8, 3);
    Sbit (EX1 , 0xA8, 2);
    Sbit (ET0 , 0xA8, 1);
    Sbit (EX0 , 0xA8, 0);
    
    Sfr (P3 , 0xB0);
    /* --- P3 Bits ------- */
    Sbit (RXD , 0xB0, 0);
    Sbit (TXD , 0xB0, 1);
    Sbit (INT0 , 0xB0, 2);
    Sbit (INT1 , 0xB0, 3);
    Sbit (T0 , 0xB0, 4);
    Sbit (T1 , 0xB0, 5);
    Sbit (WR , 0xB0, 6);
    Sbit (RD , 0xB0, 7);
    /* ---  P3 Bits --- */
    Sbit (P3_0 , 0xB0, 0);
    Sbit (P3_1 , 0xB0, 1);
    Sbit (P3_2 , 0xB0, 2);
    Sbit (P3_3 , 0xB0, 3);
    Sbit (P3_4 , 0xB0, 4);
    Sbit (P3_5 , 0xB0, 5);
    Sbit (P3_6 , 0xB0, 6);
    Sbit (P3_7 , 0xB0, 7);
    
    Sfr (IPL0 , 0xB8);
    /* --- IPL0 Bits ----- */
    Sbit (PPCL , 0xB8, 6);
    Sbit (PT2L , 0xB8, 5);
    Sbit (PSL , 0xB8, 4);
    Sbit (PT1L , 0xB8, 3);
    Sbit (PX1L , 0xB8, 2);
    Sbit (PT0L , 0xB8, 1);
    Sbit (PX0L , 0xB8, 0);
    
    Sfr (P4 , 0xC0);
    /* ---  P4 Bits --- */
    Sbit (SCL , 0xC0, 0);
    Sbit (SDA , 0xC0, 1);
    Sbit (ALE , 0xC0, 4);
    Sbit (PSENB , 0xC0, 5);
    /* ---  P4 Bits --- */
    Sbit (P4_0 , 0xC0, 0);
    Sbit (P4_1 , 0xC0, 1);
    Sbit (P4_2 , 0xC0, 2);
    Sbit (P4_3 , 0xC0, 3);
    Sbit (P4_4 , 0xC0, 4);
    Sbit (P4_5 , 0xC0, 5);
    Sbit (P4_6 , 0xC0, 6);
    Sbit (P4_7 , 0xC0, 7);
    
    Sfr (T2CON , 0xC8);
    /* --- T2CON bits ---- */
    Sbit (TF2 , 0xC8, 7);
    Sbit (EXF2 , 0xC8, 6);
    Sbit (RCLK , 0xC8, 5);
    Sbit (TCLK , 0xC8, 4);
    Sbit (EXEN2 , 0xC8, 3);
    Sbit (TR2 , 0xC8, 2);
    Sbit (C_T2 , 0xC8, 1);
    Sbit (CP_RL2 , 0xC8, 0);
    
    Sfr (PSW , 0xD0);
    /* --- PSW bits ------ */
    Sbit (CY , 0xD0, 7);
    Sbit (AC , 0xD0, 6);
    Sbit (F0 , 0xD0, 5);
    Sbit (RS1 , 0xD0, 4);
    Sbit (RS0 , 0xD0, 3);
    Sbit (OV , 0xD0, 2);
    Sbit (P , 0xD0, 0);
    
    Sfr (CCON , 0xD8);
    /* --- CCON bits ----- */
    Sbit (CF , 0xD8, 7);
    Sbit (CR , 0xD8, 6);
    Sbit (CCF4 , 0xD8, 4);
    Sbit (CCF3 , 0xD8, 3);
    Sbit (CCF2 , 0xD8, 2);
    Sbit (CCF1 , 0xD8, 1);
    Sbit (CCF0 , 0xD8, 0);
    
    Sfr (ACC , 0xE0);
    Sfr (B , 0xF0);
    
    Sfr (SP , 0x81);
    Sfr (DPL , 0x82);
    Sfr (DPH , 0x83);
    Sfr (DP0L , 0x82);
    Sfr (DP0H , 0x83);
    /*Sfr (CKSEL , 0x85);*/
    /*Sfr (OSCCON , 0x86)*/
    Sfr (PCON , 0x87);
    
    Sfr (TMOD , 0x89);
    Sfr (TL0 , 0x8A);
    Sfr (TL1 , 0x8B);
    Sfr (TH0 , 0x8C);
    Sfr (TH1 , 0x8D);
    Sfr (AUXR , 0x8E);
    Sfr (CKCON0 , 0x8F);
    
    Sfr (TCONB , 0x91);
    Sfr (BMSEL , 0x92);
    Sfr (SSCON , 0x93);
    Sfr (SSCS , 0x94);
    Sfr (SSDAT , 0x95);
    Sfr (SSADR , 0x96);
    Sfr (CKRL , 0x97);
    
    Sfr (SBUF , 0x99);
    Sfr (BRL , 0x9A);
    Sfr (BDRCON , 0x9B);
    Sfr (KBLS , 0x9C);
    Sfr (KBE , 0x9D);
    Sfr (KBF , 0x9E);
    Sfr (KBMO , 0x9F);
    
    Sfr (DPCF , 0xA1);
    Sfr (AUXR1 , 0xA2);
    Sfr (ACSRA , 0xA3);
    Sfr (DADC , 0xA4);
    Sfr (DADI , 0xA5);
    Sfr (WDTRST , 0xA6);
    Sfr (WDTPRG , 0xA7);
    
    Sfr (SADDR , 0xA9);
    Sfr (ACSRB , 0xAB);
    Sfr (DADL , 0xAC);
    Sfr (DADH , 0xAD);
    Sfr (CLKEG , 0xAE);
    Sfr (CKCON1 , 0xAF);
    
    Sfr (IEN1 , 0xB1);
    Sfr (IPL1 , 0xB2);
    Sfr (IPH1 , 0xB3);
    Sfr (IPH0 , 0xB7);
    
    Sfr (SADEN , 0xB9);
    Sfr (AREF , 0xBD);
    Sfr (P4M0 , 0xBE);
    Sfr (P4M1 , 0xBF);
    
    Sfr (SPCON , 0xC3);
    Sfr (SPSTA , 0xC4);
    Sfr (SPDAT , 0xC5);
    Sfr (P3M0 , 0xC6);
    Sfr (P3M1 , 0xC7);
    
    Sfr (T2MOD , 0xC9);
    Sfr (RCAP2L , 0xCA);
    Sfr (RCAP2H , 0xCB);
    Sfr (TL2 , 0xCC);
    Sfr (TH2 , 0xCD);
    Sfr (P2M0 , 0xCE);
    Sfr (P2M1 , 0xCF);
    
    Sfr (FCON , 0xD1);
    Sfr (EECON , 0xD2);
    Sfr (DPLB , 0xD4);
    Sfr (DPHB , 0xD5);
    Sfr (DP1L , 0xD4);
    Sfr (DP1H , 0xD5);
    Sfr (P1M0 , 0xD6);
    Sfr (P1M1 , 0xD7);
    
    Sfr (CMOD , 0xD9);
    Sfr (CCAPM0 , 0xDA);
    Sfr (CCAPM1 , 0xDB);
    Sfr (CCAPM2 , 0xDC);
    Sfr (CCAPM3 , 0xDD);
    Sfr (CCAPM4 , 0xDE);
    
    Sfr (AX , 0xE1);
    Sfr (DSPR , 0xE2);
    Sfr (FIRD , 0xE3);
    Sfr (MACL , 0xE4);
    Sfr (MACH , 0xE5);
    Sfr (P0M0 , 0xE6);
    Sfr (P0M1 , 0xE7);
    
    Sfr (CL , 0xE9);
    Sfr (CCAP0L , 0xEA);
    Sfr (CCAP1L , 0xEB);
    Sfr (CCAP2L , 0xEC);
    Sfr (CCAP3L , 0xED);
    Sfr (CCAP4L , 0xEE);
    Sfr (SPX , 0xEF);
    
    Sfr (RL0 , 0xF2);
    Sfr (RL1 , 0xF3);
    Sfr (RH0 , 0xF4);
    Sfr (RH1 , 0xF5);
    Sfr (PAGE , 0xF6);
    Sfr (BX , 0xF7);
    
    Sfr (CH , 0xF9);
    Sfr (CCAP0H , 0xFA);
    Sfr (CCAP1H , 0xFB);
    Sfr (CCAP2H , 0xFC);
    Sfr (CCAP3H , 0xFD);
    Sfr (CCAP4H , 0xFE);
    

    C code:

    #include ".\teste.h"
    #include <AT89LP51RD2.h>
    #include <stdlib.h>
    #include <stdint.h>
    
    // Uncomment line below to skip static & global variable initialization
    // int _sdcc_external_startup() { return 1;}
    
    void main(void)
    {
        volatile int16_t aaa, bbb, ccc;
    
        aaa = 0x11;
        bbb = 0x22;
    
        while(1)
        {
            ccc = aaa * bbb;
            aaa ++;
            bbb --;
            ccc = 0;
        }
    
    }
    

    Disassembly

    0000: 02 00 08          LJMP  0x0008     
    0003: 12 00 64          LCALL ??0009     
    0006: 80 fe             SJMP  0x0006    
    0008: 75 81 0f          MOV   SP, #0x0F
    000b: 12 00 bd          LCALL ??000c     
    000e: e5 82             MOV   A, DPL
    0010: 60 03             JZ    ??0000    
    0012: 02 00 03          LJMP  0x0003     
    0015: 79 00     ??0000: MOV   R1, #0x00
    0017: e9                MOV   A, R1  
    0018: 44 00             ORL   A, #0x00
    001a: 60 1b             JZ    ??0003    
    001c: 7a 00             MOV   R2, #0x00
    001e: 90 00 c1          MOV   DPTR, #0x00C1
    0021: 78 00             MOV   R0, #0x00
    0023: 75 a0 00          MOV   P2, #0x00
    0026: e4        ??0001: CLR   A      
    0027: 93                MOVC  A, @A+DPTR
    0028: f2                MOVX  @R0, A 
    0029: a3                INC   DPTR    
    002a: 08                INC   R0     
    002b: b8 00 02          CJNE  R0, #0x00, ??0002 
    002e: 05 a0             INC   P2   
    0030: d9 f4     ??0002: DJNZ  R1, ??0001 
    0032: da f2             DJNZ  R2, ??0001 
    0034: 75 a0 ff          MOV   P2, #0xFF
    0037: e4        ??0003: CLR   A      
    0038: 78 ff             MOV   R0, #0xFF
    003a: f6        ??0004: MOV   @R0, A 
    003b: d8 fd             DJNZ  R0, ??0004 
    003d: 78 00             MOV   R0, #0x00
    003f: e8                MOV   A, R0  
    0040: 44 00             ORL   A, #0x00
    0042: 60 0a             JZ    ??0006    
    0044: 79 00             MOV   R1, #0x00
    0046: 75 a0 00          MOV   P2, #0x00
    0049: e4                CLR   A      
    004a: f3        ??0005: MOVX  @R1, A 
    004b: 09                INC   R1     
    004c: d8 fc             DJNZ  R0, ??0005 
    004e: 78 00     ??0006: MOV   R0, #0x00
    0050: e8                MOV   A, R0  
    0051: 44 00             ORL   A, #0x00
    0053: 60 0c             JZ    ??0008    
    0055: 79 00             MOV   R1, #0x00
    0057: 90 00 00          MOV   DPTR, #0x0000
    005a: e4                CLR   A      
    005b: f0        ??0007: MOVX  @DPTR, A
    005c: a3                INC   DPTR    
    005d: d8 fc             DJNZ  R0, ??0007 
    005f: d9 fa             DJNZ  R1, ??0007 
    0061: 02 00 03  ??0008: LJMP  0x0003     
    0064: 75 08 11  ??0009: MOV   08, #0x11
    0067: 75 09 00          MOV   09, #0x00
    006a: 75 0a 22          MOV   0A, #0x22
    006d: 75 0b 00          MOV   0B, #0x00
    0070: 85 0a 0e          MOV   0E, 0A
    0073: 85 0b 0f          MOV   0F, 0B
    0076: 85 08 82          MOV   DPL, 08
    0079: 85 09 83          MOV   DPH, 09
    007c: 12 00 a0          LCALL ??000b     
    007f: 85 82 0c          MOV   0C, DPL
    0082: 85 83 0d          MOV   0D, DPH
    0085: 74 01             MOV   A, #0x01 
    0087: 25 08             ADD   A, 08 
    0089: f5 08             MOV   08, A
    008b: e4                CLR   A      
    008c: 35 09             ADDC  A, 09 
    008e: f5 09             MOV   09, A
    0090: 15 0a             DEC   0A   
    0092: 74 ff             MOV   A, #0xFF 
    0094: b5 0a 02          CJNE  A, 0A, ??000a   
    0097: 15 0b             DEC   0B   
    0099: e4        ??000a: CLR   A      
    009a: f5 0c             MOV   0C, A
    009c: f5 0d             MOV   0D, A
    009e: 80 d0             SJMP  0x0070    
    00a0: e5 82     ??000b: MOV   A, DPL
    00a2: 85 0e f0          MOV   B, 0E
    00a5: a4                MUL   AB      
    00a6: c5 82             XCH   A, DPL
    00a8: c0 f0             PUSH  B   
    00aa: 85 0f f0          MOV   B, 0F
    00ad: a4                MUL   AB      
    00ae: d0 f0             POP   B    
    00b0: 25 f0             ADD   A, B 
    00b2: c5 83             XCH   A, DPH
    00b4: 85 0e f0          MOV   B, 0E
    00b7: a4                MUL   AB      
    00b8: 25 83             ADD   A, DPH 
    00ba: f5 83             MOV   DPH, A
    00bc: 22                RET          
    00bd: 75 82 00  ??000c: MOV   DPL, #0x00
    00c0: 22                RET          
    

    It seems that they are using the standard MUL.

    I will try what you said. However, getting the result from the M register seems to be a little bit tricky

     
  • Maarten Brock

    Maarten Brock - 2017-04-20

    AFAIK the Atmel version of SDCC is identical to our 2.9.0 version with only added header files.

     

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