I am writing a C program for an emulated 80c51 chip on a FPGA, which is currently still being done in assembly.
I have all features like serial communication, CANbus and timer routines working but one. The external interrupt.
The external interrupts work different than on a real 80c51. To begin we have 8 interrupts, all on port P1. The problem I am having is that I dont know to work arround the specific syntax used for the ISR. I mean this:
void timer0 (void) __interrupt 1
{
}
The interrupt 1 (and __interrupt 4 for the serial one)
I know that these interrupts 1 and 4 point to addresses 0x0b and 0x23 respectively but I do not know how or where this happens. The only references I could find in all used software is in the bottem of at89x51.h
But they are just simple defines and not sfr and this does not do anything for me.
We use special bits to configure the interrupt. The only respons I have so far is that triggering the I/O pin disables my timer and possibly also the serial interrupts. And my co-worker confirmed that I am setting the bits fine. The problem is that the ISR doesn't get called. I tried using __interrupt 0 which is at address 0x03
But no luck. I simply don't know how the system works between these numbered interrupts and the address pointing. Is this cooked in SDCC?? I also tried pulling some information out of the generated .asm file but so far I have not been able to find what I am looking for.
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I used SDCC with stm8 a bit, but I could find vector table in more human-readable format in .rst file not in .asm (produced when linking, with absolute addresses). As I understand the associations between interrupt number and address are hardcoded in SDCC (maybe it can be changed but I don't know how to do this).
Sample from .rst file:
38 .area HOME
008000 39 __interrupt_vect:
008000 82 00 80 3B 40 int s_GSINIT ; reset
008004 82 00 00 00 41 int 0x0000 ; trap
008008 82 00 00 00 42 int 0x0000 ; int0
00800C 82 00 00 00 43 int 0x0000 ; int1
008010 82 00 00 00 44 int 0x0000 ; int2
008014 82 00 00 00 45 int 0x0000 ; int3
008018 82 00 00 00 46 int 0x0000 ; int4
00801C 82 00 00 00 47 int 0x0000 ; int5
008020 82 00 00 00 48 int 0x0000 ; int6
008024 82 00 00 00 49 int 0x0000 ; int7
008028 82 00 00 00 50 int 0x0000 ; int8
00802C 82 00 00 00 51 int 0x0000 ; int9
008030 82 00 00 00 52 int 0x0000 ; int10
008034 82 00 80 58 53 int _TIM1_UPDOVF_IRQ_Handler ; int11
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There is little to fear. The 8051 architecture reserves 3 bytes at the start for an LJMP, then there are small (8 bytes) code blocks reserved for each IRQ. Usually these also contain a LJMP but very small IRQ routines might fit in there too.
It would be extremely unusual for an 8051 FPGA implementation to break the assumption cited in your original post "address = (number * 8) + 3". In fact it could be argued that this should not be called a 8051 implementation any more.
So you should be fine by just specifying the matching IRQ number:
It seems to me that the part you do not understand should be in the documentation for the fpga implementation of the 8051. You say you have 8 external interrupts. According to the documentation what should happen when, say, the first is triggered? To what vector is the core supposed to jump? And for the second? And the last?
The 'hardcoded' vectors in sdcc are there because (almost) every 8051 has them hardcoded that way.
Last edit: Maarten Brock 2017-12-28
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
I am writing a C program for an emulated 80c51 chip on a FPGA, which is currently still being done in assembly.
I have all features like serial communication, CANbus and timer routines working but one. The external interrupt.
The external interrupts work different than on a real 80c51. To begin we have 8 interrupts, all on port P1. The problem I am having is that I dont know to work arround the specific syntax used for the ISR. I mean this:
The interrupt 1 (and __interrupt 4 for the serial one)
I know that these interrupts 1 and 4 point to addresses 0x0b and 0x23 respectively but I do not know how or where this happens. The only references I could find in all used software is in the bottem of at89x51.h
But they are just simple defines and not sfr and this does not do anything for me.
We use special bits to configure the interrupt. The only respons I have so far is that triggering the I/O pin disables my timer and possibly also the serial interrupts. And my co-worker confirmed that I am setting the bits fine. The problem is that the ISR doesn't get called. I tried using __interrupt 0 which is at address 0x03
But no luck. I simply don't know how the system works between these numbered interrupts and the address pointing. Is this cooked in SDCC?? I also tried pulling some information out of the generated .asm file but so far I have not been able to find what I am looking for.
I forgor the attachment
I used SDCC with stm8 a bit, but I could find vector table in more human-readable format in .rst file not in .asm (produced when linking, with absolute addresses). As I understand the associations between interrupt number and address are hardcoded in SDCC (maybe it can be changed but I don't know how to do this).
Sample from .rst file:
this is what I feared :( thanks for your reply
There is little to fear. The 8051 architecture reserves 3 bytes at the start for an LJMP, then there are small (8 bytes) code blocks reserved for each IRQ. Usually these also contain a LJMP but very small IRQ routines might fit in there too.
It would be extremely unusual for an 8051 FPGA implementation to break the assumption cited in your original post "address = (number * 8) + 3". In fact it could be argued that this should not be called a 8051 implementation any more.
So you should be fine by just specifying the matching IRQ number:
this gives you, looking at the .rst file as Nikolay proposed:
In the very strange case that this does not match your hardware, you do not yet have to give up.
The table is generated in line 226 here:
https://sourceforge.net/p/sdcc/code/HEAD/tree/trunk/sdcc/src/mcs51/main.c
If you should need to adapt, please report back.
It seems to me that the part you do not understand should be in the documentation for the fpga implementation of the 8051. You say you have 8 external interrupts. According to the documentation what should happen when, say, the first is triggered? To what vector is the core supposed to jump? And for the second? And the last?
The 'hardcoded' vectors in sdcc are there because (almost) every 8051 has them hardcoded that way.
Last edit: Maarten Brock 2017-12-28