robert - 2008-11-30

I am new to this architecture so the breadth of this atomic complication causes me serious concern.  I am looking for some advice to minimize impact on code size and performance while still keeping the system stable.  To me, it seems like non-atomic operations are so common that turning interrupts on and off around each case will impact both size and performance.

I am thinking it may be more wise to make the ISRs protect/restore context.  It seems then the first thing to do is organize code into three sets of registers – set0 for normal code, set1 for low priority interrupts and set2 for high priority interrupts.  That may well take care of most issues (I am guessing).  Additionally then if, ACC, B, DPTR, and some PSW flags are all restored by the interrupt, then interrupts might not need to be shut off all the time.

I haven’t found any good advice on the web – what sort of strategies have you guys used successfully?