#3670 read_cdb_file always assigns var to "rom" without considering banking

[mark]

hey,

When simulating banked code in ucsim 0.8.2, with the following config file -

set memory xram 0xffff 0x00
memory create banker xram 0xffff 0x7 rom 0x1d00 0xffff
memory create chip big_rom 0x80000 8
memory create bank rom 0x1d00 0 big_rom 0x01d00
memory create bank rom 0x1d00 1 big_rom 0x11d00
memory create bank rom 0x1d00 2 big_rom 0x21d00
memory create bank rom 0x1d00 3 big_rom 0x31d00
memory create bank rom 0x1d00 4 big_rom 0x41d00
memory create bank rom 0x1d00 5 big_rom 0x51d00
memory create bank rom 0x1d00 6 big_rom 0x61d00
memory create bank rom 0x1d00 7 big_rom 0x71d00
load "output/firmware_merged.hex"
load "output/firmware.cdb"

- I see wrong labels in the code dump.

0> set memory xram 0xffff 0x00
0> dc 0x1d00

0x1d00    <CEepromWriteVersion>:
0x1d00  ? 75 08 68 MOV    0x08,#0x68
0x1d03  ? 74 08    MOV    A,#0x08
0x1d05  ? c0 e0    PUSH   0xe0 <ACC>

0> set memory xram 0xffff 0x01
0xffff                                        01 .

0> dc 0x1d00
0x1d00    <CEepromWriteVersion>:
0x1d00  ? af 83    MOV    R7,0x83 <DPH>
0x1d02  ? e5 82    MOV    A,0x82 <DPL>
0x1d04  ? 90 fb b7 MOV    DPTR,#0xfbb7

As you can see, location 0x1d00 of rom is labelled "CEepromWriteVersion" which comes directly from the line in the cdb: L:G$CEepromWriteVersion$0$0:1D00

However, when the bank is set to 1, the underlying location in the ihx (big_rom) is 0x011d00 and the appropriate label from the cdb is: L:G$SetOsdMap$0$0:11D00.

I can solve this by
1) adding chip_begin=banks[b]->chip_begin; to the end of cl_banker::activate, which makes ad->as_to_chip(space_addr) work correctly
2) updating cl_vars_iterator::first with this:

         if (vars->by_addr.search(chip_mem, chip_addr, chip_i))
            chip_var = vars->by_addr.at(chip_i);
         else if (vars->by_addr.search(space_mem, chip_addr, space_i))
            space_var = vars->by_addr.at(space_i);

which checks space_mem (rom) where the variables are imported to by "load".

I don't know enough about the code / running the tests to say whether that could have unintended bad effects.

like, maybe the variables should be created in chip_mem in the first place, and then only the first fix would be required(?)

Cheers.
Mark

[mark]

1) adding chip_begin=banks[b]->chip_begin; to the end of cl_banker::activate, which makes ad->as_to_chip(space_addr) work correctly

actually the start:

  if (banks[b] == NULL)
    return true;

  chip_begin=banks[b]->chip_begin;

  if (b == bank)
    return true;