#2221 fix for mcs51 psw optimisation bug

[Alex Burton]

Background:
The mcs51 arcitecture allows interrupt service routines to use different register banks. This is done by setting the value of the PSW register at the start of the ISR.
The mcs51 code gen attempts to eliminate the instruction that sets the PSW when it thinks no registers have been used, so the register bank switch is unneccessary.

Problem:
In the case where the ISR doesn't use any registers but calls other functions that do use registers, elimination is performed, resulting in corruption of the registers used by the interrupted code.

Fix:
The attached patch checks to see if the ISR calls anything else before eliminating instruction to set the ISR.

[Alex Burton]

A patch to fix psw optimisation bug in /mcs51/gen.c

[Maarten Brock]

Is there a bug report that this patch is trying to fix? Or do you have an example of failing code?

[Alex Burton]

failing code

[Alex Burton]

Attached failing code.
To see error:
Complile : sdcc test.c
open test.asm
observe "eliminated unneeded mov psw" in Timer0_ISR
observe that calculate and calculateISR both use the same registers in different banks, without the move PSW,0x080 at the start of the ISR, they will both be using the registers in bank 0, which will result in corruption of calculate in main loop.

[Maarten Brock]

Ticket moved from /p/sdcc/patches/207/

Can't be converted:

• _milestone:

Though it really is a patch the lack of a corresponding bug report made me move this item to the bug tracker. This makes it easier to relate it to the regression test file bug2221.c that will be created for this fix.

[Maarten Brock]

Patch applied in SDCC #8863.

[Maarten Brock]

I've reopened this bug because it reappeared but now caused by the register tracking functions:
; genFromRTrack removed mov psw,#0x08

[Oleg Endo]

Seems to be not a problem anymore on current SVN r14334