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SC_CoSiM is a platform which focuses on validating a full system, by performing near real-time, command-to-command co-simulation of the hardware DUT implemented on FPGA as a full system prototype (with CPU, on-chip interconnect, memory, application, drivers, and OS, typically Linux) against its equivalent cycle-approximate system-level model of the DUT.
Our work presented at DVCon-Europe 2018 extended the technology demonstrator from David C Black(https://github.com/dcblack/technology_demonstrator).
To reference this work:
A. Papagrigoriou, M.D. Grammatikakis, V. Piperaki, “A hybrid channel for co-simulation of behavioral SystemC IP with its full system prototype on FPGA”, Design Verification in Europe, Munich, Germany, October 23-25 2018, pp. 1-9. Available from
http://events.dvcon.org/Europe/2018/proceedings/papers/02_3.pdf
Features
- SystemC
- Hardware co-simulation
- Hardware co-validation
- synthesis
- ARM
- zedboard
- FPGA
