[Sbcl-commits] CVS: sbcl/src/runtime x86-64-arch.h, 1.12, 1.13 x86-arch.h, 1.17, 1.18

[Gábor M. <me...@us...>]

Update of /cvsroot/sbcl/sbcl/src/runtime
In directory fdv4jf1.ch3.sourceforge.com:/tmp/cvs-serv23922/src/runtime

Modified Files:
	x86-64-arch.h x86-arch.h 
Log Message:
1.0.24.32: undo parts of 1.0.24.26

No need for memory barriers when unlocking a spinlock on x86/x86-64.
The ordering rules and the cache coherency mechanism together
guarantee this. However, the compiler must be prevented from
reordering instructions with the unlock (at least in one direction).
This is now done in the runtime, but not in Lisp as the Lisp compiler
does no reordering.


Index: x86-64-arch.h
===================================================================
RCS file: /cvsroot/sbcl/sbcl/src/runtime/x86-64-arch.h,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- x86-64-arch.h	9 Jan 2009 16:43:56 -0000	1.12
+++ x86-64-arch.h	11 Jan 2009 15:56:03 -0000	1.13
@@ -18,7 +18,8 @@
  * here? (The answer wasn't obvious to me when merging the
  * architecture-abstracting patches for CSR's SPARC port. -- WHN 2002-02-15) */
 
-#include "interr.h"
+#define COMPILER_BARRIER \
+    do { __asm__ __volatile__ ( "" : : : "memory"); } while (0)
 
 static inline void
 get_spinlock(volatile lispobj *word,long value)
@@ -49,6 +50,15 @@
 #endif
 }
 
+static inline void
+release_spinlock(volatile lispobj *word)
+{
+    /* See comment in RELEASE-SPINLOCK in target-thread.lisp. */
+    COMPILER_BARRIER;
+    *word=0;
+    COMPILER_BARRIER;
+}
+
 static inline lispobj
 swap_lispobjs(volatile lispobj *dest, lispobj value)
 {
@@ -61,12 +71,4 @@
     return old_value;
 }
 
-static inline void
-release_spinlock(volatile lispobj *word)
-{
-    /* A memory barrier is needed, use swap_lispobjs. See comment in
-     * RELEASE-SPINLOCK in target-thread.lisp. */
-    swap_lispobjs(word,0);
-}
-
 #endif /* _X86_64_ARCH_H */

Index: x86-arch.h
===================================================================
RCS file: /cvsroot/sbcl/sbcl/src/runtime/x86-arch.h,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- x86-arch.h	9 Jan 2009 16:43:56 -0000	1.17
+++ x86-arch.h	11 Jan 2009 15:56:03 -0000	1.18
@@ -18,7 +18,8 @@
  * here? (The answer wasn't obvious to me when merging the
  * architecture-abstracting patches for CSR's SPARC port. -- WHN 2002-02-15) */
 
-#include "interr.h"
+#define COMPILER_BARRIER \
+    do { __asm__ __volatile__ ( "" : : : "memory"); } while (0)
 
 static inline void
 get_spinlock(volatile lispobj *word, unsigned long value)
@@ -48,7 +49,14 @@
 #endif
 }
 
-#include <stdio.h>
+static inline void
+release_spinlock(volatile lispobj *word)
+{
+    /* See comment in RELEASE-SPINLOCK in target-thread.lisp. */
+    COMPILER_BARRIER;
+    *word=0;
+    COMPILER_BARRIER;
+}
 
 static inline lispobj
 swap_lispobjs(volatile lispobj *dest, lispobj value)
@@ -68,14 +76,6 @@
     return old_value;
 }
 
-static inline void
-release_spinlock(volatile lispobj *word)
-{
-    /* A memory barrier is needed, use swap_lispobjs. See comment in
-     * RELEASE-SPINLOCK in target-thread.lisp. */
-    swap_lispobjs(word,0);
-}
-
 extern void fast_bzero_detect(void *, size_t);
 extern void (*fast_bzero_pointer)(void *, size_t);