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:::vhdl
signal TXDATi : std_logic_vector(DAT_O'Range);
alias TXRDYi : std_logic is TXDATi(14);
signal RXDATi : std_logic_vector(DAT_I'Range);
alias RXRDYi : std_logic is RXDATi(15);

'''vhdl
signal TXDATi : std_logic_vector(DAT_O'Range);
alias TXRDYi : std_logic is TXDATi(14);
signal RXDATi : std_logic_vector(DAT_I'Range);
alias RXRDYi : std_logic is RXDATi(15);

´´´vhdl
signal TXDATi : std_logic_vector(DAT_O'Range);
alias TXRDYi : std_logic is TXDATi(14);
signal RXDATi : std_logic_vector(DAT_I'Range);
alias RXRDYi : std_logic is RXDATi(15);