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This project is implementation of the concept presented in the paper: https://ieeexplore.ieee.org/document/5231896
Please refer to the paper for more details on design and architecture of the simulator.

The available source code files in this project are in Visual Studio 2008 Solution package.

We wrote this project in 2009 for our final Computer Engineering thesis and my recollection of the implementation is now very scarce. I'm just sharing it to supplement the theorical constructs explained in the respective IEEE paper (link above). The project as of now is in Alpha stage but, not being actively developed and maintained.

The project was meant for:

• Designing framework for simulating a custom x86 based multi-core microprocessor
• Simulating the execution of assembly level program by graphically depicting the flow of information within simulated CPU’s registers
• Support for Assembler and CPU, custom feature addition

Feature Set:

• General Purpose, Segment Registers (Real Mode Memory Operation) and Special Purpose x86-64 Registers
• Extendable x86 instruction set
• Custom Multi-Core Microprocessor Designing
• Configurable and Programmable Assembler Design
• Command Line Based Output Display Unit
• Modifiable Processor Support
• Configurable Assembler
• Multi-Core Programming Support
• Focus on simulating the working of register set and instruction set only and ignoring other components of the microprocessor (Branch Predictors, Cache Memory, FPU Unit, Pipeline Unit etc.)
• Implemented in C++ deploying object-oriented principles

Built on:
- 8086 Microprocessor Architecture and Instruction Set
- Microsoft Visual C++ 2008 (runtime libraries are probably required to execute the attached binaries)

Project Applications:
- Teaching aid for assembly programming
- Learning microprocessor operation and implementation
- Demonstrating Multi-Core Programming concepts

Future Scope / Simulator can be extended to add new features:
- Floating Point Execution Unit
- SIMD SSE Instruction Sets
- Protected Mode Memory Operations
- Cache Memory
- GUI Output Display Unit

How to run the simulator:
- Enter the number of processor cores to simulate and for each core, provide the path of file where sample assembly program is saved and the program will show the step by step change in processor register states of all the cores.

Project Admins:

• Arvind K Sharma