Working as been progressing steadily and there are still some tasks needed to be done.
Latests stats show that the kernel itself requires about 6 KiB of RAM (mainly because of 256 priority levels) and the HAL (hw related stuff) for Cortex R5 takes about 22 KiB (currently, but can still be reduced).
These values are even lower than our expectations!
The RAM needed for HAL stuff is expected to be even lower in Cortex-M than in Cortex-R, hence we are now thinking of porting Pharos also for a M0+ board with only 20 KiB of RAM!
The port to R5 was relatively easy, involing some more complex changes from the original ARM926 MMU to the R5 MPU. But the overall CPU architecture remained the same (ARM ISA) so there were no major modifications required.
The port to M4 requires more changes since it uses Thumb ISA instead of ARM ISA. However, since both the M4 and R5 use a very similar MPU, no big changes are expected here.
After M4, we have some ideas of where to go next, but would appreciate some feedback!
You could reply on this forum or just send us a private email to rtos.pharos@outlook.com.
Thank you for your time
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Now that the port for ARM Cortex-R5 and Cortex-M4 is completed, we feel it is time to move on to more powerfull CPUs.
We are thinking of doing the 1.4.0 version with the Cortex-A53 CPU. The same CPU used in Raspberry PI3. We will start "slow" with a single-core application and then move to a multi-core. Using the 64-bit CPU with a large RAM Space and the memory protection (MMU) given by armv8-a will give Pharos applications a boost in performace.
For later releases, we are considering RISC-V, Power Arch, i386. We are still deciding where to go next. Inputs would be helpfull.
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The port to Cortex-A53 is on its way to get done. Apart from some issues related to the hw (we are porting to the qemu raspberry pi3 where the documentation is scarse), the port is going well.
Now its time to think about the next CPU. Pharos has already a good support for ARM architectures (ARM9, Cortex-R, Cortex-M, Cortex-A - armv8-a). We have are minds leaning towards the RISC-V as a way of demonstrating that Pharos can be easily ported to other architectures. RISC-V is an open instruction set architecture which we feel matches with the Pharos open-source mind-set. We hope that to create a good match.
Given the lack of cost-friendly boards with MMU and some needed hardware (see https://sourceforge.net/p/rtospharos/wiki/Board%20minimum%20requirements/) we are now checking out qemu or other simulators.
Feel free to give some inputs.
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We have just release 1.5.0 version. This includes multicore support for the raspberry pi3 (Cortex-A53) in a "AMP fashion" (each core runs "separately" from each other).
Now our effort are focused on a STM32 board (https://www.st.com/en/evaluation-tools/32f469idiscovery.html). It contains a Cortex-M4 CPU with different memory areas (CCM, SRAM, SRAM backup, SDRAM) which will help to upgrade Pharos to support several memory areas for each partition.
After this release of the STM32 board (1.6.0), we are thinking about adding multicore communication services between partitions running on different cores.
Feel free to give some inputs.
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Anonymous
Anonymous
-
2020-04-12
x86 paltform support ?????
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We are taking so long to moderate the comments that we just allowed everyone to post any comment, without any moderation.
If we detect an "evil" post (like child pornography, etc) then we will delete it (or something similar). But by default anyone can now post without moderation.
Thank you
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Hello to all,
This discussion is to help decide which are the next CPUs to be supported by Pharos.
We have our eyes set on a Cortex R5 and a Cortex M4 boards.
What should be our next targets?
We are currently porting Pharos to a Cortex-R5 to a TI board, "Hercules TMS570LC43x LaunchPad Development Kit"
http://www.ti.com/tool/LAUNCHXL2-570LC43
Working as been progressing steadily and there are still some tasks needed to be done.
Latests stats show that the kernel itself requires about 6 KiB of RAM (mainly because of 256 priority levels) and the HAL (hw related stuff) for Cortex R5 takes about 22 KiB (currently, but can still be reduced).
These values are even lower than our expectations!
The RAM needed for HAL stuff is expected to be even lower in Cortex-M than in Cortex-R, hence we are now thinking of porting Pharos also for a M0+ board with only 20 KiB of RAM!
We believe NUCLEO-L073RZ from ST could be a good option (has MPU, good flash size, etc).
http://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-l073rz.html
Hello again,
Pharos 1.1.0 was released with the port for Cortex-R5 with a TI board: http://www.ti.com/tool/LAUNCHXL2-570LC43.
We are now focusing on an Cortex-M4 board, specifically the http://www.ti.com/tool/EK-TM4C129EXL board again from Texas Instruments.
The port to R5 was relatively easy, involing some more complex changes from the original ARM926 MMU to the R5 MPU. But the overall CPU architecture remained the same (ARM ISA) so there were no major modifications required.
The port to M4 requires more changes since it uses Thumb ISA instead of ARM ISA. However, since both the M4 and R5 use a very similar MPU, no big changes are expected here.
After M4, we have some ideas of where to go next, but would appreciate some feedback!
You could reply on this forum or just send us a private email to rtos.pharos@outlook.com.
Thank you for your time
Hello,
Now that the port for ARM Cortex-R5 and Cortex-M4 is completed, we feel it is time to move on to more powerfull CPUs.
We are thinking of doing the 1.4.0 version with the Cortex-A53 CPU. The same CPU used in Raspberry PI3. We will start "slow" with a single-core application and then move to a multi-core. Using the 64-bit CPU with a large RAM Space and the memory protection (MMU) given by armv8-a will give Pharos applications a boost in performace.
For later releases, we are considering RISC-V, Power Arch, i386. We are still deciding where to go next. Inputs would be helpfull.
Hello all,
The port to Cortex-A53 is on its way to get done. Apart from some issues related to the hw (we are porting to the qemu raspberry pi3 where the documentation is scarse), the port is going well.
Now its time to think about the next CPU. Pharos has already a good support for ARM architectures (ARM9, Cortex-R, Cortex-M, Cortex-A - armv8-a). We have are minds leaning towards the RISC-V as a way of demonstrating that Pharos can be easily ported to other architectures. RISC-V is an open instruction set architecture which we feel matches with the Pharos open-source mind-set. We hope that to create a good match.
Given the lack of cost-friendly boards with MMU and some needed hardware (see https://sourceforge.net/p/rtospharos/wiki/Board%20minimum%20requirements/) we are now checking out qemu or other simulators.
Feel free to give some inputs.
Hello all,
We have just release 1.5.0 version. This includes multicore support for the raspberry pi3 (Cortex-A53) in a "AMP fashion" (each core runs "separately" from each other).
Now our effort are focused on a STM32 board (https://www.st.com/en/evaluation-tools/32f469idiscovery.html). It contains a Cortex-M4 CPU with different memory areas (CCM, SRAM, SRAM backup, SDRAM) which will help to upgrade Pharos to support several memory areas for each partition.
After this release of the STM32 board (1.6.0), we are thinking about adding multicore communication services between partitions running on different cores.
Feel free to give some inputs.
x86 paltform support ?????
Hi,
Sorry for taking so long to approve your comment, I did not noticed it before :S
We can port to x86, we have so many things to do that we just don't have the time now so we currently mark it with a low priority.
Thanks for your input
Hi all,
We are taking so long to moderate the comments that we just allowed everyone to post any comment, without any moderation.
If we detect an "evil" post (like child pornography, etc) then we will delete it (or something similar). But by default anyone can now post without moderation.
Thank you