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#2 Wrong PIP equality

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nobody
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5
2012-09-18
2011-11-03
Eduardo Lezcano
No

On file attached do -xdl2ncd and you obtain an error: 2 nets want to use the same PIP:

net "Mmult_t_mult0000_Madd_3"
pip INT_X32Y106 WS2END2 -> SL2BEG1 ,

and

net "Mmult_t_mult0000_Madd_6"
pip INT_X32Y106 SW2END2 -> SL2BEG1 ,

The bug is that RapidSmith do not recognice this pips as same resource but Xilinx tools do...
I think is due to "SW" and "WS" on SW2END2 wire on wire enumerator.

Regards.
Eduardo L.A.

Discussion

  • Eduardo Lezcano

    Eduardo Lezcano - 2011-11-03

    Xdl file with the mentioned error.

     
    element1_2.xdl

  • Eduardo Lezcano

    Eduardo Lezcano - 2011-11-04

    I don't know if this is really a bug. The error may be caused by the use of SL2BEG1 instead of hole PIP. What do you think? How wires are parsed in RS? SW is equal to WS?

     

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