On Fri, Sep 6, 2013 at 11:37 AM, Soeren D. Schulze
<soeren.d.schulze@...> wrote:
> Hi everyone,
>
> as described before, I'm currently refactoring Qucs' transient solver
> into an updatebased scheme in order to overcome difficulties with small
> step sizes and (therefore) badlyconditioned Jacobians (see the branch
> "numerical_improvements"). I'm almost done; only the
> "transientCapacitance*" functions still need to be ported.
>
> From reading the source code, this is how _I understand_ them.
>
> * "transientCapacitance" computes a nonlinear capacitance Q=f(V), where
> V is the voltage across the capacitor plates.
>
> * "transientCapacitanceC" computes a linear capacitance Q=C*V, where V
> may be a voltage somewhere else in the circuit.
>
> * "transientCapacitanceQ" computes Q=f(t), i.e., a charge that doesn't
> depend on any voltage.
>
> * In Veriloggenerated code, the latter two are used together in order
> to model a general nonlinear capacitance Q=f(V), where V may, again, be
> anywhere in the circuit.
>
> Is this correct?
>
> "transientCapacitance" and "transientCapacitanceQ" currently use a
> "qstate" to save the charge; in order to port them, I'm going to turn
> this into a state variable in the x vector (if we eventually use a
> sparsematrix representation, this won't be a speed issue at all).
>
> Does anyone have an insight in the Veriloggenerated components? I'm
> not sure how to test my changes.
i second here. i want to port to recent inverter admsxml and I wish if
it is possible to get some use case with abort/assert in order to test
regression during porting
>
>
> Sören
>
> 
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