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Re: [Qucs-help] Problems with the "Build Verilog A module ..." included in QUCS 0.0.18
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From: Guilherme B. T. <gui...@gm...> - 2014-05-14 21:58:11
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Hello, These bugs seem to be fixed on the master branch. Please `git pull` and try to build/install it again. Cheers, Guilherme On 5/14/14, 10:59 PM, Guilherme Brondani Torri wrote: > Hi Jose, > > Please reply also to the list, so others can also read. > > Thank you for reporting, you just found two bugs. > > For the first I have to take a look on the code. The export feature is > a recent contribution. > https://sourceforge.net/p/qucs/bugs/154/ > > For the second there is a workaround. Do not use the `_` in the > Verilog-A file/module names for the moment. > https://sourceforge.net/p/qucs/bugs/155/ > > I will see what I can do to fix these bugs. > > Regards, > Guilherme > > On 5/14/14, 10:16 PM, Jose Manuel Campelo wrote: >> Hello again Guilherme: >> >> Thank you very much for your answer. >> >> As you told me in your last e-mail, I have tested the piece of >> Verilog-A including your comments, and it was built without any problem. >> >> After building the module, I have created a symbol for it. I have >> exported an image in .PNG format, and finally I was able to load the >> module with no problem. >> After that in the components menu, it appears a new tab that contains >> the module that I have built. >> Here comes the problem. When I want to choose the symbol for >> including it in a schematic, an error messages is shown in a window, >> saying "File not found". And just after that, the program crashes and >> closes with no further warnings. >> >> All the files of the compilation and building process, are located in >> /home/.qucs/Verilog_A_test_prj >> >> I don't know if that issue could be a bug in the program or it is >> related with something in the tree of the project. >> >> Another thing that I would like to comment is that I realized that if >> you have the Verilog-A modules in the active tab of the program, and, >> by mistake, you choose "Export Image" in the File menu, the program >> closes without any warning. >> >> I don't know if there is something wrong on my side. >> >> Can you help me? >> >> Thank you very much for your patience. >> Best regards.. >> >> >> >> > Date: Fri, 9 May 2014 09:44:16 +0200 >> > From: gui...@gm... >> > To: quc...@li... >> > Subject: Re: [Qucs-help] Problems with the "Build Verilog A module >> ..." included in QUCS 0.0.18 >> > >> > Hi Jose, >> > >> > Comments below. >> > >> > On 5/8/14, 11:14 PM, Jose Manuel Campelo wrote: >> > > Hello everybody: >> > > Recently I have installed (in UBUNTU 12.04) from the master >> branch of the git repository the last version of QUCS, the 0.0.18 >> issue.I have been "playing" with the new capability of QUCS. The one >> related to building Verilog A module and I have found several error >> messages that I do not understand. >> > > First of all I want to set clear where all the QUCS components >> are installed. Perhaps the problem is provoked by some missing path >> during the compiling process or something like that: >> > > The software is installed in the folder: /usr/local/bin/The >> "qucs-core" is installed in the folder: /usr/local/include/qucs-core >> > >> > Not really, this directory include are all the headers and xml scripts >> > required to run admsXml and compile dynamic libraries. Qucs and >> > Qucusator (found in qucs-core) applicatios should be in the >> /usr/local/bin/ >> > >> > > During the installation everything seemed to be OK. I have been >> working with SPICE models in schematics and I don't have found any >> problem. >> > >> > Good to know that it is working. We had some bugs fixed a few weeks >> ago. >> > >> > > I have tried to compile and build a very simple module in Verilog >> A. The following: >> > > `include "disciplines.vams"`include "constants.vams"module >> gain_block(in, out); inout in, out; electrical in, out; parameter >> real gain = 2.0; >> > > analog >> > > V(out) <+ V(in)*gain; >> > > endmodule >> > <snip> >> > >> > Can you try with `analog begin ... end`, the following works on my >> side. >> > >> > `include "disciplines.vams" >> > >> > `include "constants.vams" >> > >> > module gain_block(in, out); >> > >> > inout in, out; >> > >> > electrical in, out; >> > >> > parameter real gain = 2.0; >> > >> > analog begin >> > >> > V(out) <+ V(in)*gain; >> > >> > end >> > >> > endmodule >> > >> > >> > > >> > > I would like to know two things: >> > > >> > > >> > > 1.- What are those errors? What am I doing wrong? >> > >> > The errors you saw are due to fact that admsXml only supports a subset >> > of the Verilog-A language. We are working to improve that. For the >> > moment you can look at ~/qucs-core/src/components/verilog/*.va to >> check >> > what language constructs are currently used with success in Qucs. >> > >> > > 2.- If everything goes OK during the building (i.e, eventually, >> when those errors are debugged), what are the next steps? >> > >> > After the model is built, you have to create a symbol, assign an icon >> > and load the new components. Then you can use it on your schematics. >> > Have a look at slides 49-53 of: >> > >> http://www.mos-ak.org/london_2014/presentations/09_Mike_Brinson_MOS-AK_London_2014.pdf >> > > >> > > Thank you very much for your support.Best regards. >> > > >> > > >> > >> > Regards, Guilherme >> > >> ------------------------------------------------------------------------------ >> > Is your legacy SCM system holding you back? Join Perforce May 7 to >> find out: >> > • 3 signs your SCM is hindering your productivity >> > • Requirements for releasing software faster >> > • Expert tips and advice for migrating your SCM now >> > http://p.sf.net/sfu/perforce >> > _______________________________________________ >> > Qucs-help mailing list >> > Quc...@li... >> > https://lists.sourceforge.net/lists/listinfo/qucs-help > |