Now I get 0.0.16 worked
but all i get from the vhdl stimulation is that "wrong dependency"
here is the code I used for test
entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
architecture OR_arch of OR_ent is
- compare to truth table
if ((x='0') and (y='0')) then
F <= '0';
F <= '1';
architecture OR_beh of OR_ent is
F <= x or y;
the out put f is "wrong dependency"
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