I wonder if there is a mistake on my side? I couldn't use (the default) VHDL for simulation of basics gates. Google found out for me that I am not the only one, and suggested Verilog instead. Fine until today. Today I tried the basic RS-FF from the digital components, 2 digital sources, that's all. All of a sudden, Verilog runs circles doing just that:
creating netlist… done.
running VerilogHDL conversion… done.
, while VHDL, after an enormous investment into time (some 10 seconds) brings out the basic truth table.
Therefore, don't give up yet, with either. Just try the other version!
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