Jonas - 2009-09-28

Hello

I tried to make digital simulation with a VHDL file which has a std_logic_vector defined in the entity, but I got this error :

digi.vhdl: in TestBench(Arch_TestBench):
digi.vhdl:101: net_net1 does not match required type std_logic_vector (NATURAL 6 downto 0), its type could be:
/usr/share/freehdl/lib/ieee/std_logic_1164.vhdl:72:    std_logic
v2cc: digi.vhdl: 1 errors

I looked into the netlist and I found that in the code automatically generated by qucs, there was something wrong :

It is written :
architecture Arch_TestBench of TestBench is
  signal net_net0 : std_logic;
  signal net_net1 : std_logic;
begin
(…)

Instead of :
architecture Arch_TestBench of TestBench is
  signal net_net0 : std_logic;
  signal net_net1 : std_logic_vector(6 downto 0);
begin
(…)

The full netlist ist here : http://www.datafilehost.com/download-7a04ed18.html

And the vhdl file here : http://www.datafilehost.com/download-05f11870.html