#67 simulation from lib gives garbage in digi.vhdl

closed-fixed
None
5
2011-03-01
2010-04-19
gatisg
No

Picking an element patgen from my_test library (attached) and simulating it gives a win error dialogue
"freehdl-v2cc.exe has encountered a problem and ..." with options Debug/SendErrorReport/DontSend.
Simulation errors:
---------------------------------
digi.vhdl: at top level:
digi.vhdl:65: syntax error, unexpected t_Identifier at C
v2cc: digi.vhdl: 1 errors
---------------------------------
because in netlist (see below) somehow is inserted full path to element from library:
C:/Home/.qucs/user_lib/my_test/patgen.vhdl

Netlist file:
--------------------------------------------
-- Qucs 0.0.15 C:/Home/.qucs/VHDL-BADGEN_prj/tst_lib_patgen.sch
library ieee;
use ieee.std_logic_1164.all;
entity patgen is
generic ( delay : time := 0ns );
port( RESET, CLOCK: in std_logic;
Q0, Q1, Q2, Q3: out std_logic );
end entity patgen;
--
architecture beh_patgen of patgen is
begin
P1: process (RESET,CLOCK) is
variable present_state, next_state: std_logic_vector(3 downto 0) := "0000";
begin
if ( RESET = '1' ) then next_state := "0000";
elsif ( CLOCK'event and CLOCK = '1' ) then
present_state := next_state;
case present_state is
when "000Z" => next_state := "00Z1";
when "00Z1" => next_state := "0Z1Z";
when "0Z1Z" => next_state := "Z1Z0";
when "Z1Z0" => next_state := "1Z0Z";
when "1Z0Z" => next_state := "Z0Z1";
when "Z0Z1" => next_state := "0Z1Z";
when others => next_state := "000Z";
end case;
end if ;
Q3 <= next_state(3);
Q2 <= next_state(2);
Q1 <= next_state(1);
Q0 <= next_state(0);
end process P1;
end architecture beh_patgen;

library ieee;
use ieee.std_logic_1164.all;
entity Sub_my_test_patgen is
port (net_net0 : in std_logic;
net_net1 : in std_logic;
net_outnet_net2 : out std_logic;
net_outnet_net3 : out std_logic;
net_outnet_net4 : out std_logic;
net_outnet_net5 : out std_logic);
end entity;
use work.all;
architecture Arch_Sub_my_test_patgen of Sub_my_test_patgen is
signal net_net2 : std_logic;
signal net_net3 : std_logic;
signal net_net4 : std_logic;
signal net_net5 : std_logic;
begin
net_outnet_net2 <= net_net2 or '0';
net_outnet_net3 <= net_net3 or '0';
net_outnet_net4 <= net_net4 or '0';
net_outnet_net5 <= net_net5 or '0';
U1: entity patgen generic map (0ns) port map (net_net0, net_net1, net_net2, net_net3, net_net4, net_net5);
end architecture;

library ieee;
use ieee.std_logic_1164.all;
entity TestBench is
end entity;
use work.all;
C:/Home/.qucs/user_lib/my_test/patgen.vhdl

architecture Arch_TestBench of TestBench is
signal netin_CLOCK : std_logic;
signal netin_RESET : std_logic;
signal netout_Q0 : std_logic;
signal netout_Q1 : std_logic;
signal netout_Q2 : std_logic;
signal netout_Q3 : std_logic;
begin

S1:process
begin
netin_CLOCK <= '0'; wait for 10 ns;
netin_CLOCK <= '1'; wait for 10 ns;
end process;

S2:process
begin
netin_RESET <= '1'; wait for 20 ns;
netin_RESET <= '0'; wait for 1000 ns;
end process;
SUB1: entity Sub_my_test_patgen port map (netin_RESET, netin_CLOCK, netout_Q0, netout_Q1, netout_Q2, netout_Q3);
end architecture;
--------------------------------------------

Discussion

  •  gatisg

    gatisg - 2010-04-19
     
    Attachments
  • Stefan Jahn

    Stefan Jahn - 2010-04-20
    • assigned_to: nobody --> ela
     
  • Stefan Jahn

    Stefan Jahn - 2010-04-20

    Hello! As far I can see the file is correctly included in your VHDL netlist. Only, that the full filename still occurs for some reason in the netlist once again. Is this correct?

    I'll check and try to fix this bug...

    Best regards, Stefan.

     
  •  gatisg

    gatisg - 2010-04-21

    Yes, file is included in VHDL netlist plus full filename too...

    Kind regards ~
    Gatis

     
  • Stefan Jahn

    Stefan Jahn - 2011-03-01

    The bug has been fixed in CVS. Thanks for reporting it.

     
  • Stefan Jahn

    Stefan Jahn - 2011-03-01
    • status: open --> closed-fixed
     

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