#66 incorrect signal value conversation

closed-fixed
None
5
2010-05-09
2010-04-19
gatisg
No

1. See pattern generator code in patgen.vhdl
2. Testing generator in tst_vhdl_patge.sch gives results as expected (see tst_vhdl_patgen.dpl).
3. After placing a vhdl code into user defined symbol (patgen.sch) and simulating (tst_patge.sch), generators output signal values are changed (see tst_patgen.dpl).
By definition Z is known signal state, X - unknown.

Discussion

  •  gatisg

    gatisg - 2010-04-19
     
  • Stefan Jahn

    Stefan Jahn - 2010-04-20

    Hello! This is due to the fact, that std_logic signal are uninitialized in the very beginning. The difference between the 2 schematics (with and w/o subcircuit) is just an additional output buffer for outgoing signal within the subcircuit, e.g.

    net_outnet_net2 <= net_net2 or '0';

    net_net2 ist then mapped to the original VHDL patgen entity.

    I guess, with proper initialization there won't be any differences anymore. What do you think?

    Best regards, Stefan.

     
  •  gatisg

    gatisg - 2010-04-22

    Hi!

    I'm sorry - actually did not get idea - with proper initialization of ...
    Mapping is done by QUCS and it adds those "or '0'" so IMHO problem is right there, because seems like for FreeHDL 'Z' or '0' = 'X'.
    But VHDL mapping to sch should not change output signal values and in schematic symbol encapsulated VHDL should work right as VHDL.

    Kind regards ~
    Gatis

     
  • Stefan Jahn

    Stefan Jahn - 2010-04-22

    Hello Gatis, when I checked the problem I saw your observation as well. "or '0'" is to blame. I guess leaving the statement without "or '0'" will solve the problem. Thanks for pointing to it.

    Best regards, Stefan.

     
  • Stefan Jahn

    Stefan Jahn - 2010-04-22
    • assigned_to: nobody --> ela
     
  • Stefan Jahn

    Stefan Jahn - 2010-05-09

    Hello! The bug is now fixed in CVS.

     
  • Stefan Jahn

    Stefan Jahn - 2010-05-09
    • status: open --> closed-fixed
     

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