Looks like the code was merged on GitHub https://github.com/Qucs/qucs/commit/4f8625ef32619a650ca78d1785e684077f5aac1d Which appears to have made it here too: https://sourceforge.net/p/qucs/git/ci/4f8625ef32619a650ca78d1785e684077f5aac1d/ Glad it made it in! I agree Codeberg is good. Zig went there as a middle finger to GitHub and Microslop. My own GitHub is mostly taken down now because of all the LLMs not respecting licenses. Have had a go with Gitea and Codeberg. It's nice in a way; git was made...
Looks like the code was merged on GitHub https://github.com/Qucs/qucs/commit/4f8625ef32619a650ca78d1785e684077f5aac1d Which appears to have made it here too: https://sourceforge.net/p/qucs/git/ci/4f8625ef32619a650ca78d1785e684077f5aac1d/ Glad it made it in! I agree Codeberg is good. Zig went there as a middle finger to GitHub and Microslop. My own GitHub is mostly taken down now because of all the LLMs not respecting licenses. Have had a go with Gitea and Codeberg. It's nice in a way; git was made...
Looks like the code was merged on GitHub https://github.com/Qucs/qucs/commit/4f8625ef32619a650ca78d1785e684077f5aac1d Which appears to have made it here too: https://sourceforge.net/p/qucs/git/ci/4f8625ef32619a650ca78d1785e684077f5aac1d/ Glad it made it in! I agree Codeberg is good. Zig went there as a middle finger to GitHub and Microslop. My own GitHub is mostly taken down now because of all the LLMs not respecting licenses. Have had a go with Gitea and Codeberg. It's nice in a way; git was made...
Looks like the code was merged on GitHub https://github.com/Qucs/qucs/commit/4f8625ef32619a650ca78d1785e684077f5aac1d Which appears to have made it here too: https://sourceforge.net/p/qucs/git/ci/4f8625ef32619a650ca78d1785e684077f5aac1d/ Glad it made it in! I agree Codeberg is good. Zig went there as a middle finger to GitHub and Microslop. My own GitHub is mostly taken down now because of all the LLMs not respecting licenses. Have had a go with Gitea and Codeberg. It's nice in a way; git was made...
On Wed, Mar 25, 2026 at 01:29:27AM -0000, artsurd wrote: I haven't used SourceForge like this before, but thought I'd give it a go. I've also made the same request on GitHub in case this is the wrong place. Thanks. Since you raised it. I am not sure why the code was moved got github, probably just for the "git workflow". Today Codeberg might be a much better option, but I only recently created [1]. I will look at your patch when I find some time. [1] https://codeberg.org/qucs/gui
GitHub PR: https://github.com/Qucs/qucs/pull/1116
Here is the patch: From 4f8625ef32619a650ca78d1785e684077f5aac1d Mon Sep 17 00:00:00 2001 From: artsurd <git@artsurd.info> Date: Wed, 25 Mar 2026 01:08:00 +0000 Subject: [PATCH] Fix use after free in qucsMessageOutput --- qucs/main.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qucs/main.cpp b/qucs/main.cpp index 0a50bd8d6..8879f84eb 100644 --- a/qucs/main.cpp +++ b/qucs/main.cpp @@ -37,7 +37,9 @@ */ void qucsMessageOutput(QtMsgType type, const QMessageLogContext &, const...
Here is the patch.
Fix use after free in qucsMessageOutput
fix: Prevent segfault in Schematic::newMovingWires
Merge 'lupdate'
Also check for lupdate-qt5
add CONTRIBUTE
use default compiler in AC_PROG_CXX
Please have a look at this schematic attached to this post. I have built this circuit in real ife, and it does what it is supposed to do. A low on ENABLE_TX_12V results in +12V on RX_12V, a high on ENABLE_TX_12V reslts in 0V on RX_12V. I tried to simulate this behaviour in QUCS, but could not get it right, Possibly model files for the 2N7002 and IRF4905 are wrong, so I replaced them with generic nMOS and pMOS devices available in QUCS. Simulation says it is successful, but in the graph nothing appears....
Please have a look at this schematic attached to this post. I have built this circuit in real ife, and it does what it is supposed to do. A low on ENABLE_TX_12V results in +12V on RX_12V, a high on ENABLE_TX_12V reslts in 0V on RX_12V. I tried to simulate this behaviour in QUCS, but could not get it right, Possiblyy model files for the 2N7002 and IRF4905 are wrong, so I replaced them with generic nMOS and pMOS devices available in QUCS. Simulation says it is successful, but in the graph nothing appears....
Hello everyone, My name is Jesús Everardo, and I am developing a Python module that acquires real-time S-parameters from the NanoVNA (S11/S21), performs frequency sweeps, and exports Touchstone and CSV files. I would like to integrate this functionality into Qucs/Qucs-S either as an extension, a measurement component, or an external interface to enable direct visualization and analysis of the measurements within the simulator. I would greatly appreciate any guidance on how to connect this data with...
Merge Turkish translations update
Fix typo in translation for number of copies
Update Turkish translations in qtgeneric_tr.ts
Refine Turkish translations in qtgeneric_tr.ts
Is there a version for Apple Silicone. I have a Mac Mini M4.
improve wire label dump/parse
fix port access in position dump
fix position in graphics item dump
dump wire labels as nodes
cleanup Schematic::dumpVerilogComponent
fix comment
bump ref. missing connections
Reading Verilog: Wire labels
Update Tests: Verilog Dump
Verilog Dump: Dump Wire Label position
net label test
fix indent. went wrong in 386426dd8eaf
Removing unused code
test status
Parse attribut DRY fix
Merge preamble
Introducing preample loading
Fix DRY violation
Element "center and relative boundings" are private
Merge experimental Verilog-S dump/load
Verilog Parsing: Parse visibility
Regenerating Verilog Schematics
create sch and vs round trip diffs during tests
superficial testing
Verilog Schematic: Visibility of properties
Paintings: Introducing setter and getter for attributes
sync ctos with gnucap/develop & test
fix S__text type
ROADMAP, TODO update
cleanup prj_log_compiler
Verilog Dump: Painting/GraphicText dumping
Updating the Verilog schematics
bugfix lang_verilog. always prefer qucs_type attribute
fix include in lang_verilog
errors and warnings in component
Adding integrity check
Add label name getter method
Write nodes out as wires
fix compile warnings, add Wire::port
Add a warn method to Schematic
Add nodename_at function
Adding set_port_by index functionality
Bug fix: Solving save-as issue
Bugfix: Open .vs files as schematic
fix qt rules in various qucs-*/Makefile.am
Merge 'comp_loading'
Using dump/parse identifier from Gnucap
missing lib test
Positioning components without ports
more cleanup
Move code over to correct compilation unit
smart pointer conversion fix
Merge wire_cleanup
cleanup node interface a bit
missing test file
split off LegacyComponent
move up "Component" class
prepare Wire ports cleanup
hello world ngspice
hello world example
more Verilog_File cleanup and disentangle
"Verilog" device. initial fixes
some more parameters are attributes
Makefile fixes
Merge wire placement
Initial code for wire placement
Component placement
Merge 'lib'
cleanup/fix Sub
cleanup/fix Lib
more
Merge read_verilog
fix parameter parsing
fix out of range Props access, try #2
Solve crash when dumping netlists/fix refs
fix compile warnings
Solving uninitialized value warning
cleanup, disentangle dumpDeclaration