When resetting the dds the processor is not stable
because the clock is switched during the program. About
ecery 10th write the processor just doesn't output
anything at all, but it sends the correct ptp replies.
This is expected behavior, since the DDS supplies the clock
for the processor. That's why the reset has to be generated
by an I2C line and not one of the FPGA outputs. I propose
the following solution: remove the DDS reset
from api.py:begin_sequence, put it in a separate function,
and make a special script which is only run once every time
the hardware is powered up (or undergoes a hard reset).
That way, the DDS sync clock will always be stable in
between program writes.
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This is expected behavior, since the DDS supplies the clock
for the processor. That's why the reset has to be generated
by an I2C line and not one of the FPGA outputs. I propose
the following solution: remove the DDS reset
from api.py:begin_sequence, put it in a separate function,
and make a special script which is only run once every time
the hardware is powered up (or undergoes a hard reset).
That way, the DDS sync clock will always be stable in
between program writes.