[ps2hacking-devel] r5900_flush_cache_sigtramp() Inquiry

[Paul M. <pm...@mv...>]

Hello,

During my venture in rewriting the r5900 MM code (look for it in the linux-=
mips
CVS sometime soon), I became a little bit curious about a specific portion =
of
the code.. namely the r5900_flush_cache_sigtramp() code.

The R5900 is the only processor that deals with flushing both the beginning=
 and
the end of the icache and dcache regions.. everyone else simply flushes out
from the start address, is there any reason for this?

Ideally, replacing the whole thing with something like:

	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
	protected_flush_icache_line(addr & ~(ic_lsize - 1));

where the icache and dcache line sizes are fixed at 64 bytes, should work.

If this isn't the case, can someone shed some light on the situation? Or am
I just totally missing something obvious?

Regards,

--=20
Paul Mundt <pm...@mv...>
MontaVista Software, Inc.