From: Pekka J. <pek...@tu...> - 2011-12-15 19:17:54
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On 12/15/2011 09:04 PM, Erik Schnetter wrote: > supports the half datatype How do you think so? http://llvm.org/docs/LangRef.html#t_floating As I wrote, I think it's supported only via those two conversion intrinsics: http://llvm.org/docs/LangRef.html#int_fp16 My question was that who implements those intrinsics (fp32 to fp16 to fp32) as they require some bit manipulation of the fp fields, AFAIK (extract mantissa, exponent, sign and put them pack to the destination) and it's unlikely the hardware has direct instructions for such conversion. Do you mean that the default lowering of those intrinsics produces the conversion code too? Using native halfs would mean that one can use smaller adders, multipliers, shifters etc. in the FPUs which means energy savings in low power designs (less switching activity). Too bad it seems not to be supported yet in LLVM, AFAIU. -- --Pekka |