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[liudawei <dbm...@ya...>]

I have done a simple test  step by step according your suggestion ,but unfortunely I encountered another problem. Let me descirbe my test here.
  step 1. I edit the configure file "papi3_itanium2.xml",just keep two entries left.
  papi3_itanium2.xml is my default configure file.I just let this file only includes two entry according your suggestion.The contents is here.
-------------------------------------------------------------------------------------------------------------
<?xml version="1.0" encoding="UTF-8"?>
<ps_hwpc_eventlist class="PAPI" generator="psconfig">
  <ps_hwpc_event type="preset" name="PAPI_TOT_CYC" />
  <ps_hwpc_event type="preset" name="PAPI_TOT_INS" />
</ps_hwpc_eventlist>
-------------------------------------------------------------------------------------------------------------
step 2. I write a simple C program name "a.c" then I compile it into a executeble named "a.out".
step 3. I start my test work via the command "psrun a.out",then an expected file is gotted.
step 4. I use psrpocess to process this file via the command "a.out.27000.Node4.xml". I list the results as follows. The results is what I am expecting, just as you say, the "Total cycles" and "Instructions completed" are all not zero. I continue do my test work, pls see the step 5.
  ---------------------------------------------------------------------------------------------------------------
  PerfSuite Hardware Performance Summary Report
  Version                      : 1.0
Created                      : Fri Jan 12 10:57:12 AM CST 2007
Generator                    : psprocess 0.3
XML Source                   : a.out.25984.Node4.xml
  Execution Information
============================================================================================
Collector                    : libpshwpc
Date                         : Fri Jan 12 10:56:49 2007
Host                         : Node4
User                         : root
Command                      : a.out
  Processor and System Information
============================================================================================
Node CPUs                    : 2
Vendor                       : Intel
Family                       : Itanium 2
CPU Revision                 : 2
Clock (MHz)                  : 1600.030
Memory (MB)                  : 4032.42
Pagesize (KB)                : 16
  Cache Information
============================================================================================
Cache levels                 : 3
--------------------------------
Level 1
Type                         : data
Size (KB)                    : 16
Linesize (B)                 : 64
Assoc                        : 4
Type                         : instruction
Size (KB)                    : 16
Linesize (B)                 : 64
Assoc                        : 4
--------------------------------
Level 2
Type                         : unified
Size (KB)                    : 256
Linesize (B)                 : 128
Assoc                        : 8
--------------------------------
Level 3
Type                         : unified
Size (KB)                    : 3072
Linesize (B)                 : 128
Assoc                        : 6
  Index Description                                                              Counter Value
============================================================================================
    1 Total cycles.....................................................                36270
    2 Instructions completed...........................................                25558
  Event Index
============================================================================================
    1: PAPI_TOT_CYC        2: PAPI_TOT_INS
  Statistics
============================================================================================
Counting domain........................................................                 user
Multiplexed............................................................                   no
Graduated instructions per cycle.......................................                0.705
MIPS (cycles)..........................................................             1127.476
MIPS (wall clock)......................................................              747.215
CPU time (seconds).....................................................                0.000
Wall clock time (seconds)..............................................                0.000
% CPU utilization......................................................               66.273
------------------------------------------------------------------------------------------------------------------
step 5. I edit the "papi3_itanium2.xml" and added another entry(say, I want to know the total numbers of  L1 data cache misses ). The configure file which is listed here again
---------------------------------------
<?xml version="1.0" encoding="UTF-8"?>
<ps_hwpc_eventlist class="PAPI" generator="psconfig">
  <ps_hwpc_event type="preset" name="PAPI_L1_DCM" />
  <ps_hwpc_event type="preset" name="PAPI_TOT_CYC" />
  <ps_hwpc_event type="preset" name="PAPI_TOT_INS" />
</ps_hwpc_eventlist>
------------------------------------------------------------------------
step 6: psrun a.out
step 7: psprocess a.out.27020.Node4.xml
I got a result once more, this time I got the total numbers of L1 data cache misses caused by a.out. This results is also I expected. So I continue my work.
step 8: "vi papi3_itanium2.xml" to added another entry which is an events I interested.
so the configure file contents like this
--------------------------------------------------------
 <?xml version="1.0" encoding="UTF-8"?>
<ps_hwpc_eventlist class="PAPI" generator="psconfig">
  <ps_hwpc_event type="preset" name="PAPI_L1_DCM" />
  <ps_hwpc_event type="preset" name="PAPI_L2_ICM" />
  <ps_hwpc_event type="preset" name="PAPI_TOT_CYC" />
  <ps_hwpc_event type="preset" name="PAPI_TOT_INS" />
 </ps_hwpc_eventlist>
-----------------------------------------------------
step 9: psprocess a.out.27038.Node4.xml
but this time I did not got the results I expected. The results are list here. What is wrong with my work? The zero result are not expected.
----------------------------------------------------------------------------------------
PerfSuite Hardware Performance Summary Report
  Version                      : 1.0
Created                      : Fri Jan 12 03:39:48 PM CST 2007
Generator                    : psprocess 0.3
XML Source                   : a.out.27038.Node4.xml
  Execution Information
===========================================================================================
Collector                    : libpshwpc
Date                         : Fri Jan 12 15:39:35 2007
Host                         : Node4
User                         : telnet
Command                      : a.out
  Processor and System Information
===========================================================================================
Node CPUs                    : 2
Vendor                       : Intel
Family                       : Itanium 2
CPU Revision                 : 2
Clock (MHz)                  : 1600.030
Memory (MB)                  : 4032.42
Pagesize (KB)                : 16
  Cache Information
===========================================================================================
Cache levels                 : 3
--------------------------------
Level 1
Type                         : data
Size (KB)                    : 16
Linesize (B)                 : 64
Assoc                        : 4
Type                         : instruction
Size (KB)                    : 16
Linesize (B)                 : 64
Assoc                        : 4
--------------------------------
Level 2
Type                         : unified
Size (KB)                    : 256
Linesize (B)                 : 128
Assoc                        : 8
--------------------------------
Level 3
Type                         : unified
Size (KB)                    : 3072
Linesize (B)                 : 128
Assoc                        : 6
  Index Description
ounter Value
===========================================================================================
    1 Level 1 data cache misses........................................0
    2 Level 2 instruction cache misses.................................0
    3 Total cycles.....................................................0
    4 Instructions completed...........................................0
  Event Index
===================================================================================
    1: PAPI_L1_DCM         2: PAPI_L2_ICM         3: PAPI_TOT_CYC        4: PAP_TOT_INS
  Statistics
===========================================================================================
Counting domain........................................................        user
Multiplexed............................................................         yes
MIPS (wall clock)......................................................       0.000
CPU time (seconds).....................................................       0.000
Wall clock time (seconds)..............................................       0.000
% CPU utilization......................................................       0.000
  ------------------------------------------------------------------------------------------------------------------step 10: I use  "psinv -p " to see the availble events of my machine.
  PAPI Standard Event Details -
Non-derived:
        PAPI_BR_INS:    Branch instructions
        PAPI_BR_PRC:    Conditional branch instructions correctly predicted
        PAPI_CA_SNP:    Requests for a snoop
        PAPI_FP_OPS:    Floating point operations
        PAPI_FP_STAL:   Cycles the FP unit(s) are stalled
        PAPI_L1_DCA:    Level 1 data cache accesses
        PAPI_L1_DCM:    Level 1 data cache misses
        PAPI_L1_DCR:    Level 1 data cache reads
        PAPI_L1_ICM:    Level 1 instruction cache misses
        PAPI_L2_DCA:    Level 2 data cache accesses
        PAPI_L2_DCR:    Level 2 data cache reads
        PAPI_L2_DCW:    Level 2 data cache writes
        PAPI_L2_ICA:    Level 2 instruction cache accesses
        PAPI_L2_ICM:    Level 2 instruction cache misses
        PAPI_L2_LDM:    Level 2 load misses
        PAPI_L2_STM:    Level 2 store misses
        PAPI_L2_TCA:    Level 2 total cache accesses
        PAPI_L2_TCM:    Level 2 cache misses
        PAPI_L2_TCW:    Level 2 total cache writes
        PAPI_L3_DCA:    Level 3 data cache accesses
        PAPI_L3_DCR:    Level 3 data cache reads
        PAPI_L3_DCW:    Level 3 data cache writes
        PAPI_L3_ICA:    Level 3 instruction cache accesses
        PAPI_L3_ICH:    Level 3 instruction cache hits
        PAPI_L3_ICM:    Level 3 instruction cache misses
        PAPI_L3_ICR:    Level 3 instruction cache reads
        PAPI_L3_LDM:    Level 3 load misses
        PAPI_L3_STM:    Level 3 store misses
        PAPI_L3_TCA:    Level 3 total cache accesses
        PAPI_L3_TCM:    Level 3 cache misses
        PAPI_L3_TCR:    Level 3 total cache reads
        PAPI_L3_TCW:    Level 3 total cache writes
        PAPI_LD_INS:    Load instructions
        PAPI_RES_STL:   Cycles stalled on any resource
        PAPI_SR_INS:    Store instructions
        PAPI_STL_CCY:   Cycles with no instructions completed
        PAPI_STL_ICY:   Cycles with no instruction issue
        PAPI_TLB_DM:    Data translation lookaside buffer misses
        PAPI_TLB_IM:    Instruction translation lookaside buffer misses
        PAPI_TOT_CYC:   Total cycles
        PAPI_TOT_IIS:   Instructions issued
Derived:
        PAPI_BR_MSP:    Conditional branch instructions mispredicted
        PAPI_CA_INV:    Requests for cache line invalidation
        PAPI_L1_DCH:    Level 1 data cache hits
        PAPI_L1_ICA:    Level 1 instruction cache accesses
        PAPI_L1_ICR:    Level 1 instruction cache reads
        PAPI_L1_LDM:    Level 1 load misses
        PAPI_L1_TCA:    Level 1 total cache accesses
        PAPI_L1_TCM:    Level 1 cache misses
        PAPI_L1_TCR:    Level 1 total cache reads
        PAPI_L2_DCH:    Level 2 data cache hits
        PAPI_L2_DCM:    Level 2 data cache misses
        PAPI_L2_ICR:    Level 2 instruction cache reads
        PAPI_L2_TCH:    Level 2 total cache hits
        PAPI_L2_TCR:    Level 2 total cache reads
        PAPI_L3_DCH:    Level 3 data cache hits
        PAPI_L3_DCM:    Level 3 data cache misses
        PAPI_L3_TCH:    Level 3 total cache hits
        PAPI_TLB_TL:    Total translation lookaside buffer misses
        PAPI_TOT_INS:   Instructions completed
  ----------------------------------------------------------------------------------------------------------------
  step 11: I tried to add other events, but I got the same results. all the results are zero
  step 12: Finished.
  What is the problem happen ? Waiting your reply.
   
   
  Best Reagard
  Dawei Liu
  Renmin University of China
100872 Beijing,China

 		
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