For your consideration, I've attached a patch to fix some issues in the
POWER5 support code.
This patch is quite a lot larger than the first try. This is mostly
because I wanted to correct some unsafe practices that were used in the
original version of this code - namely that the control registers were
written in numerical order, which is not a good idea because the
counters and interrupts are enabled before the event selection is done.
Also, the mechanism by which the counters were stopped (writing all
zeroes to the control registers is not a good method because that will
not stop counters 5 & 6 on POWER5/5+ (POWER6 counters 5 & 6 cannot be
stopped using any mechanism). The correct way to disable all the
counters is to set the FC (Freeze Counters) bit in MMCRO.
To fix the problem that I was trying to fix (that counters 5 & 6 were
overflowing and not being dealt with because they are unused), I changed
it so that the get_ovfl_pmds function always zeroes out the unused
counters (5 or 6 or both). This removes them as a source of interupts
for the next 2^31 events and effectively treats interrupts from these
the unsed counter(s) as spurious and ignores them.
Please take a look and let me know if there are any problems with this.
Without this fix, the PAPI test ctests/first would cause a kernel hang
after running it 4 or 5 times, not to mention getting bogus counts on
the cycles counter about half of the time.
IBM Linux Technology Center, Linux Toolchain