Re: [perfmon2] panic on mips when using sampling
Status: Beta
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From: Ralf B. <ra...@li...> - 2007-12-13 19:05:20
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On Thu, Dec 13, 2007 at 11:58:50AM +0100, Philip Mucci wrote: > Yes, this is true for almost all MIPS processors, the interrupt is shared. > However, the timer irq code isn't unified so this one got left out. :-( > Good catch Vince. Did you send this one to Ralf B on Linux-MIPS as well? > I'll send it along to him. For 2.6.24 I've done a no prisoners taken rewrite of all the timer code, so ll_timer_interrupt does no longer exist. Classic MIPS processors always had the compare and performance counter interrupts tied to IE7 bits of c0_status / c0_cause. The E9000 core has the option to move them to one of the other interrupts but that was a PMC Sierra homebrew feature on top of their MIPS IV variant. Finally Release 2 of the MIPS Architecture specification came up with the option to allow an interrupt to be bound to an arbitrary other CPU interrupt. I'll forward your patch to the Octane people. Thanks, Ralf PS: And afair all SF mailing lists are subscriber-only posting so this one will probably bounce ... |