following is the illustration for the event "offcore_requests" on I7
Name : OFFCORE_REQUESTS
Code : 0xb0
Counters : [ 0 1 2 3 ]
Desc : All offcore requests
Umask-00 : 0x80 : [ANY] : All offcore requests
Umask-01 : 0x08 : [ANY_READ] : Offcore read requests
Umask-02 : 0x10 : [ANY_RFO] : Offcore RFO requests
Umask-03 : 0x01 : [DEMAND_READ_DATA] : Offcore demand data read requests
Umask-04 : 0x04 : [DEMAND_RFO] : Offcore demand RFO requests
Umask-05 : 0x40 : [L1D_WRITEBACK] : Offcore L1 data cache writebacks
PEBS : No
Uncore : No
why there are Umask-05 about offcore L1 data cache writebacks ?
as far as I know, I7's L1 L2 cache are on chip and private per-core,
L3 cache is off-chip and shared by all the core.