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[Pearcolator-devel] SF.net SVN: pearcolator: [138] src/org/binarytranslator/arch/arm/decoder
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From: <mic...@us...> - 2007-06-20 13:25:36
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Revision: 138
http://svn.sourceforge.net/pearcolator/?rev=138&view=rev
Author: michael_baer
Date: 2007-06-20 06:25:36 -0700 (Wed, 20 Jun 2007)
Log Message:
-----------
Thumb interpret and translator pass validating Dhrystone test.
Modified Paths:
--------------
src/org/binarytranslator/arch/arm/decoder/ARM_Instructions.java
src/org/binarytranslator/arch/arm/decoder/ARM_Interpreter.java
src/org/binarytranslator/arch/arm/decoder/ARM_Translator.java
Modified: src/org/binarytranslator/arch/arm/decoder/ARM_Instructions.java
===================================================================
--- src/org/binarytranslator/arch/arm/decoder/ARM_Instructions.java 2007-06-19 17:34:26 UTC (rev 137)
+++ src/org/binarytranslator/arch/arm/decoder/ARM_Instructions.java 2007-06-20 13:25:36 UTC (rev 138)
@@ -473,8 +473,9 @@
else {
//add/subtract register or add/subtract immediate
opcode = Utils.getBit(instr, 9) ? Opcode.SUB : Opcode.ADD;
- if (Utils.getBit(instr, 10))
+ if (Utils.getBit(instr, 10)) {
operand2 = OperandWrapper.createImmediate(Utils.getBits(instr, 6, 8));
+ }
else
operand2 = OperandWrapper.createRegister((byte)Utils.getBits(instr, 6, 8));
}
@@ -746,7 +747,7 @@
Rd = (byte)Utils.getBits(instr, 0, 2);
Rn = (byte)Utils.getBits(instr, 3, 5);
- if (Utils.getBits(instr, 13, 15) == 0x5) {
+ if (Utils.getBits(instr, 12, 15) == 0x5) {
//load store register offset
offset = OperandWrapper.createRegister((byte)Utils.getBits(instr, 6, 8));
Modified: src/org/binarytranslator/arch/arm/decoder/ARM_Interpreter.java
===================================================================
--- src/org/binarytranslator/arch/arm/decoder/ARM_Interpreter.java 2007-06-19 17:34:26 UTC (rev 137)
+++ src/org/binarytranslator/arch/arm/decoder/ARM_Interpreter.java 2007-06-20 13:25:36 UTC (rev 138)
@@ -480,7 +480,8 @@
if (i.Rn == ARM_Registers.PC) {
int value = regs.readPC();
- if (i.isThumb && !i.updateConditionCodes && i.opcode == Opcode.ADD)
+ //this is a very special instruction encoding that demands that the PC is read with an ARM32 mask.
+ if (i.isThumb && !i.updateConditionCodes && i.opcode == Opcode.ADD && i.operand2.getType() == OperandWrapper.Type.Immediate)
value = value & 0xFFFFFFFC;
return value;
@@ -504,12 +505,18 @@
*/
protected final void setAddResult(int lhs, int rhs) {
setFlagsForAdd(lhs, rhs);
-
- if (DBT_Options.profileDuringInterpretation && i.Rd == 15) {
- ps.branchInfo.registerBranch(regs.get(ARM_Registers.PC), lhs + rhs, BranchType.INDIRECT_BRANCH);
+ int result = lhs + rhs;
+
+ if (i.Rd == ARM_Registers.PC) {
+ if (regs.getThumbMode())
+ result |= 1;
+
+ if (DBT_Options.profileDuringInterpretation) {
+ ps.branchInfo.registerBranch(regs.get(ARM_Registers.PC), result, BranchType.INDIRECT_BRANCH);
+ }
}
- regs.set(i.Rd, lhs + rhs);
+ regs.set(i.Rd, result);
}
/**
@@ -520,12 +527,18 @@
*/
protected final void setSubResult(int lhs, int rhs) {
setFlagsForSub(lhs, rhs);
+ int result = lhs - rhs;
- if (DBT_Options.profileDuringInterpretation && i.Rd == 15) {
- ps.branchInfo.registerBranch(regs.get(ARM_Registers.PC), lhs - rhs, BranchType.INDIRECT_BRANCH);
+ if (i.Rd == ARM_Registers.PC) {
+ if (regs.getThumbMode())
+ result |= 1;
+
+ if (DBT_Options.profileDuringInterpretation) {
+ ps.branchInfo.registerBranch(regs.get(ARM_Registers.PC), result, BranchType.INDIRECT_BRANCH);
+ }
}
- regs.set(i.Rd, lhs - rhs);
+ regs.set(i.Rd, result);
}
/** Sets the processor flags according to the result of adding <code>lhs</code> and <code>rhs</code>.*/
Modified: src/org/binarytranslator/arch/arm/decoder/ARM_Translator.java
===================================================================
--- src/org/binarytranslator/arch/arm/decoder/ARM_Translator.java 2007-06-19 17:34:26 UTC (rev 137)
+++ src/org/binarytranslator/arch/arm/decoder/ARM_Translator.java 2007-06-20 13:25:36 UTC (rev 138)
@@ -933,7 +933,7 @@
if (i.Rn == ARM_Registers.PC) {
int value = readPC();
- if (i.isThumb && !i.updateConditionCodes && i.opcode == Opcode.ADD)
+ if (i.isThumb && !i.updateConditionCodes && i.opcode == Opcode.ADD && i.operand2.getType() == OperandWrapper.Type.Immediate)
value = value & 0xFFFFFFFC;
return new OPT_IntConstantOperand( value );
@@ -959,7 +959,7 @@
protected final void setAddResult(OPT_RegisterOperand result, OPT_Operand lhs, OPT_Operand rhs) {
if (i.updateConditionCodes) {
- if (i.Rd != 15) {
+ if (i.Rd != ARM_Registers.PC) {
setAddFlags(result, lhs, rhs);
}
else {
@@ -968,8 +968,12 @@
}
}
- if (i.Rd == 15) {
+ if (i.Rd == ARM_Registers.PC) {
+ if (inThumb()) {
+ arm2ir.appendInstruction(Binary.create(INT_OR, result.copyRO(), result.copy(), new OPT_IntConstantOperand(1)));
+ }
+
if (i.updateConditionCodes)
arm2ir.appendBranch(result, lazy, BranchType.INDIRECT_BRANCH);
else
@@ -1011,7 +1015,7 @@
protected final void setSubResult(OPT_RegisterOperand result, OPT_Operand lhs, OPT_Operand rhs) {
if (i.updateConditionCodes) {
- if (i.Rd != 15) {
+ if (i.Rd != ARM_Registers.PC) {
setSubFlags(result, lhs, rhs);
}
else {
@@ -1020,7 +1024,12 @@
}
}
- if (i.Rd == 15) {
+ if (i.Rd == ARM_Registers.PC) {
+
+ if (inThumb()) {
+ arm2ir.appendInstruction(Binary.create(INT_OR, result.copyRO(), result.copy(), new OPT_IntConstantOperand(1)));
+ }
+
if (i.updateConditionCodes)
arm2ir.appendBranch(result, lazy, BranchType.INDIRECT_BRANCH);
else
@@ -1640,7 +1649,7 @@
translateWriteback(startAddress.copyRO(), nextAddress.copyRO());
//shall we switch to thumb mode?
- OPT_BasicBlock finishInstruction = arm2ir.createBlockAfterCurrentNotInCFG();
+ /*OPT_BasicBlock finishInstruction = arm2ir.createBlockAfterCurrentNotInCFG();
OPT_BasicBlock switchToARMBlock = arm2ir.createBlockAfterCurrentNotInCFG();
OPT_BasicBlock switchToThumbBlock = arm2ir.createBlockAfterCurrentNotInCFG();
@@ -1671,6 +1680,8 @@
//according to the APCS, these types of instructions are usually function returns
arm2ir.setCurrentBlock(finishInstruction);
+ arm2ir.appendBranch(regPC, lazy, BranchType.RETURN);*/
+
arm2ir.appendBranch(regPC, lazy, BranchType.RETURN);
return;
}
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