Menu
▾
▴
[Pearcolator-devel] SF.net SVN: pearcolator: [119] ext/org/jikesrvm/compilers/opt/ia32/ OPT_BURS_Helpers.java
|
From: <mic...@us...> - 2007-05-16 18:16:19
|
Revision: 119
http://svn.sourceforge.net/pearcolator/?rev=119&view=rev
Author: michael_baer
Date: 2007-05-16 11:16:21 -0700 (Wed, 16 May 2007)
Log Message:
-----------
Changes to compile with latest JRVM
Modified Paths:
--------------
ext/org/jikesrvm/compilers/opt/ia32/OPT_BURS_Helpers.java
Modified: ext/org/jikesrvm/compilers/opt/ia32/OPT_BURS_Helpers.java
===================================================================
--- ext/org/jikesrvm/compilers/opt/ia32/OPT_BURS_Helpers.java 2007-05-16 18:15:51 UTC (rev 118)
+++ ext/org/jikesrvm/compilers/opt/ia32/OPT_BURS_Helpers.java 2007-05-16 18:16:21 UTC (rev 119)
@@ -9,11 +9,7 @@
package org.jikesrvm.compilers.opt.ia32;
import org.jikesrvm.VM;
-import org.jikesrvm.runtime.VM_Entrypoints;
-import org.jikesrvm.runtime.VM_Magic;
-import org.jikesrvm.runtime.VM_Runtime;
-import org.jikesrvm.classloader.*;
-import org.jikesrvm.compilers.opt.ir.ia32.*;
+import org.jikesrvm.classloader.VM_TypeReference;
import org.jikesrvm.compilers.opt.OPT_BURS;
import org.jikesrvm.compilers.opt.OPT_BURS_MemOp_Helpers;
import org.jikesrvm.compilers.opt.OPT_DefUse;
@@ -63,6 +59,64 @@
import org.jikesrvm.compilers.opt.ir.OPT_MethodOperand;
import org.jikesrvm.compilers.opt.ir.OPT_Operand;
import org.jikesrvm.compilers.opt.ir.OPT_Operator;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.CALL_SAVE_VOLATILE;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.DOUBLE_CMPL;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.FLOAT_CMPL;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.GUARD_MOVE;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_ADC;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_ADD;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_AND;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_BT;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_CALL;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_CDQ;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_CMOV;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_CMP;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FCMOV;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FCOMI;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FCOMIP;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FILD;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FIST;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FLD;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FLD1;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FLDCW;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FLDL2E;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FLDL2T;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FLDLG2;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FLDLN2;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FLDPI;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FLDZ;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FMOV;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FNSTCW;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FPREM;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_FSTP;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_IDIV;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_IMUL2;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_JCC;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_LOCK_CMPXCHG;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_MOV;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_MOVSX__B;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_MOVZX__B;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_MUL;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_NEG;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_NOT;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_OR;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_RCR;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_RDTSC;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_SAR;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_SBB;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_SET__B;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_SHL;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_SHLD;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_SHR;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_SHRD;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_SUB;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_SYSCALL;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_TEST;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_TRAPIF;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IA32_XOR;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.IR_PROLOGUE;
+import static org.jikesrvm.compilers.opt.ir.OPT_Operators.MIR_LOWTABLESWITCH;
+
import org.jikesrvm.compilers.opt.ir.OPT_Register;
import org.jikesrvm.compilers.opt.ir.OPT_RegisterOperand;
import org.jikesrvm.compilers.opt.ir.OPT_RegisterOperandEnumeration;
@@ -73,16 +127,15 @@
import org.jikesrvm.compilers.opt.ir.Prologue;
import org.jikesrvm.compilers.opt.ir.TrapIf;
import org.jikesrvm.compilers.opt.ir.Unary;
-
-import static org.jikesrvm.compilers.opt.ir.OPT_Operators.*;
+import org.jikesrvm.compilers.opt.ir.ia32.OPT_BURSManagedFPROperand;
+import org.jikesrvm.compilers.opt.ir.ia32.OPT_IA32ConditionOperand;
+import org.jikesrvm.runtime.VM_Entrypoints;
+import org.jikesrvm.runtime.VM_Magic;
+import org.jikesrvm.runtime.VM_Runtime;
import org.vmmagic.unboxed.Offset;
/**
* Contains IA32-specific helper functions for BURS.
- *
- * @author Dave Grove
- * @author Stephen Fink
- * @author Ian Rogers
*/
abstract class OPT_BURS_Helpers extends OPT_BURS_MemOp_Helpers {
/** Constant log10(2), supported as an x87 constant */
@@ -114,7 +167,7 @@
/**
* Follow a chain of Move operations filtering back to a def
- *
+ *
* @param use the place to start from
* @return the operand at the start of the chain
*/
@@ -146,18 +199,19 @@
/**
* Remember a condition code in a child node
- *
+ *
* @param c condition code to record
*/
protected final void pushCOND(OPT_ConditionOperand c) {
- if (VM.VerifyAssertions)
+ if (VM.VerifyAssertions) {
VM._assert(cc == null);
+ }
cc = c;
}
/**
* Acquire remembered condition code in parent
- *
+ *
* @return condition code
*/
protected final OPT_ConditionOperand consumeCOND() {
@@ -171,7 +225,7 @@
/**
* Can an IV be the scale in a LEA instruction?
- *
+ *
* @param op operand to examine
* @param trueCost the cost if this can be part of an LEA
* @return trueCost or INFINITE
@@ -182,7 +236,7 @@
/**
* Can an IV be the scale in a LEA instruction?
- *
+ *
* @param op operand to examine
* @param trueCost the cost if this can be part of an LEA
* @param falseCost the cost if this can't be part of an LEA
@@ -200,22 +254,22 @@
protected final byte LEA_SHIFT(OPT_Operand op) {
switch (IV(op)) {
- case 0:
- return B_S;
- case 1:
- return W_S;
- case 2:
- return DW_S;
- case 3:
- return QW_S;
- default:
- throw new OPT_OptimizingCompilerException("bad val for LEA shift " + op);
+ case 0:
+ return B_S;
+ case 1:
+ return W_S;
+ case 2:
+ return DW_S;
+ case 3:
+ return QW_S;
+ default:
+ throw new OPT_OptimizingCompilerException("bad val for LEA shift " + op);
}
}
/**
* Is the given instruction's constant operand a x87 floating point constant
- *
+ *
* @param s the instruction to examine
* @param trueCost the cost if this is a valid constant
* @return trueCost or INFINITE depending on the given constant
@@ -298,7 +352,7 @@
}
}
throw new OPT_OptimizingCompilerException("OPT_BURS_Helpers",
- "unexpected 387 constant " + val);
+ "unexpected 387 constant " + val);
}
protected final OPT_IA32ConditionOperand COND(OPT_ConditionOperand op) {
@@ -354,9 +408,10 @@
* Move op into a register operand if it isn't one already.
*/
private OPT_Operand asReg(OPT_Instruction s, OPT_Operator movop,
- OPT_Operand op) {
- if (op.isRegister())
+ OPT_Operand op) {
+ if (op.isRegister()) {
return op;
+ }
OPT_RegisterOperand tmp = regpool.makeTemp(op);
EMIT(CPOS(s, MIR_Move.create(movop, tmp, op)));
return tmp.copy();
@@ -364,7 +419,7 @@
/**
* Set the size field of the given memory operand and return it
- *
+ *
* @param mo memory operand size to set
* @param size the new size
* @return mo
@@ -376,7 +431,7 @@
/**
* Create a slot on the stack in memory for a conversion
- *
+ *
* @param size for memory operand
* @return memory operand of slot in stack
*/
@@ -396,21 +451,21 @@
OPT_RegisterOperand lval = new OPT_RegisterOperand(regpool
.getSecondReg(hval.register), VM_TypeReference.Int);
EMIT(MIR_Move.create(IA32_MOV, new OPT_StackLocationOperand(true,
- offset + 4, DW), hval));
+ offset + 4, DW), hval));
EMIT(MIR_Move.create(IA32_MOV, new OPT_StackLocationOperand(true, offset,
- DW), lval));
+ DW), lval));
} else {
OPT_LongConstantOperand val = LC(op);
EMIT(MIR_Move.create(IA32_MOV, new OPT_StackLocationOperand(true,
- offset + 4, DW), IC(val.upper32())));
+ offset + 4, DW), IC(val.upper32())));
EMIT(MIR_Move.create(IA32_MOV, new OPT_StackLocationOperand(true, offset,
- DW), IC(val.lower32())));
+ DW), IC(val.lower32())));
}
}
/**
* Create memory operand to load 32 bits form a given jtoc offset
- *
+ *
* @param offset location in JTOC
* @return created memory operand
*/
@@ -418,7 +473,7 @@
OPT_LocationOperand loc = new OPT_LocationOperand(offset);
OPT_Operand guard = TG();
return OPT_MemoryOperand.D(VM_Magic.getTocPointer().plus(offset), (byte) 4,
- loc, guard);
+ loc, guard);
}
/*
@@ -430,7 +485,7 @@
/**
* Emit code to get a caught exception object into a register
- *
+ *
* @param s the instruction to expand
*/
protected final void GET_EXCEPTION_OBJECT(OPT_Instruction s) {
@@ -442,7 +497,7 @@
/**
* Emit code to move a value in a register to the stack location where a
* caught exception object is expected to be.
- *
+ *
* @param s the instruction to expand
*/
protected final void SET_EXCEPTION_OBJECT(OPT_Instruction s) {
@@ -454,22 +509,22 @@
/**
* Expansion of INT_2LONG
- *
+ *
* @param s the instruction to expand
* @param result the result operand
* @param value the second operand
*/
protected final void INT_2LONG(OPT_Instruction s, OPT_RegisterOperand result,
- OPT_Operand value) {
+ OPT_Operand value) {
OPT_Register hr = result.register;
OPT_Register lr = regpool.getSecondReg(hr);
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lr,
- VM_TypeReference.Int), value));
+ VM_TypeReference.Int), value));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(hr,
- VM_TypeReference.Int),
- new OPT_RegisterOperand(lr, VM_TypeReference.Int)));
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lr, VM_TypeReference.Int)));
EMIT(MIR_BinaryAcc.create(IA32_SAR, new OPT_RegisterOperand(hr,
- VM_TypeReference.Int), IC(31)));
+ VM_TypeReference.Int), IC(31)));
}
/**
@@ -477,13 +532,13 @@
* expansion does some boolean logic and conditional moves in order to avoid
* changing the floating-point rounding mode or inserting branches. Other
* expansions are possible, and may be better?
- *
+ *
* @param s the instruction to expand
* @param result the result operand
* @param value the second operand
*/
protected final void FPR_2INT(OPT_Instruction s, OPT_RegisterOperand result,
- OPT_Operand value) {
+ OPT_Operand value) {
OPT_MemoryOperand M;
// Step 1: Get value to be converted into myFP0
@@ -500,8 +555,9 @@
// semantics before doing a particular f2int conversion. To do this
// we must have a store/load sequence to cause IEEE rounding.
if (value instanceof OPT_BURSManagedFPROperand) {
- if (VM.VerifyAssertions)
+ if (VM.VerifyAssertions) {
VM._assert(value.similar(myFP0()));
+ }
EMIT(MIR_Move.create(IA32_FSTP, MO_CONV(DW), value));
EMIT(MIR_Move.create(IA32_FLD, myFP0(), MO_CONV(DW)));
} else {
@@ -521,21 +577,27 @@
OPT_Register isPositive = regpool.getInteger();
OPT_Register isNegative = regpool.getInteger();
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(one,
- VM_TypeReference.Int), IC(1)));
+ VM_TypeReference.Int), IC(1)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(isPositive,
- VM_TypeReference.Int), IC(0)));
+ VM_TypeReference.Int), IC(0)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(isNegative,
- VM_TypeReference.Int), IC(0)));
+ VM_TypeReference.Int), IC(0)));
EMIT(MIR_Nullary.create(IA32_FLDZ, myFP0()));
// FP Stack: myFP0 = 0.0; myFP1 = value
EMIT(MIR_Compare.create(IA32_FCOMIP, myFP0(), myFP1()));
// FP Stack: myFP0 = value
- EMIT(MIR_CondMove.create(IA32_CMOV, new OPT_RegisterOperand(isPositive,
- VM_TypeReference.Int), new OPT_RegisterOperand(one,
- VM_TypeReference.Int), OPT_IA32ConditionOperand.LLT()));
- EMIT(MIR_CondMove.create(IA32_CMOV, new OPT_RegisterOperand(isNegative,
- VM_TypeReference.Int), new OPT_RegisterOperand(one,
- VM_TypeReference.Int), OPT_IA32ConditionOperand.LGT()));
+ EMIT(MIR_CondMove.create(IA32_CMOV,
+ new OPT_RegisterOperand(isPositive,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(one,
+ VM_TypeReference.Int),
+ OPT_IA32ConditionOperand.LLT()));
+ EMIT(MIR_CondMove.create(IA32_CMOV,
+ new OPT_RegisterOperand(isNegative,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(one,
+ VM_TypeReference.Int),
+ OPT_IA32ConditionOperand.LGT()));
EMIT(MIR_Move.create(IA32_FILD, myFP0(), MO_CONV(DW)));
// FP Stack: myFP0 = round(value), myFP1 = value
@@ -547,25 +609,35 @@
EMIT(MIR_Compare.create(IA32_FCOMIP, myFP0(), myFP1()));
// FP Stack: myFP0 = value
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(addee,
- VM_TypeReference.Int), IC(0)));
+ VM_TypeReference.Int), IC(0)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(subtractee,
- VM_TypeReference.Int), IC(0)));
- EMIT(MIR_CondMove.create(IA32_CMOV, new OPT_RegisterOperand(addee,
- VM_TypeReference.Int), new OPT_RegisterOperand(one,
- VM_TypeReference.Int), OPT_IA32ConditionOperand.LLT()));
- EMIT(MIR_CondMove.create(IA32_CMOV, new OPT_RegisterOperand(subtractee,
- VM_TypeReference.Int), new OPT_RegisterOperand(one,
- VM_TypeReference.Int), OPT_IA32ConditionOperand.LGT()));
+ VM_TypeReference.Int), IC(0)));
+ EMIT(MIR_CondMove.create(IA32_CMOV,
+ new OPT_RegisterOperand(addee,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(one,
+ VM_TypeReference.Int),
+ OPT_IA32ConditionOperand.LLT()));
+ EMIT(MIR_CondMove.create(IA32_CMOV,
+ new OPT_RegisterOperand(subtractee,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(one,
+ VM_TypeReference.Int),
+ OPT_IA32ConditionOperand.LGT()));
// Now a little tricky part.
// We will add 1 iff isNegative and x > round(x)
// We will subtract 1 iff isPositive and x < round(x)
- EMIT(MIR_BinaryAcc.create(IA32_AND, new OPT_RegisterOperand(addee,
- VM_TypeReference.Int), new OPT_RegisterOperand(isNegative,
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.create(IA32_AND, new OPT_RegisterOperand(subtractee,
- VM_TypeReference.Int), new OPT_RegisterOperand(isPositive,
- VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_AND,
+ new OPT_RegisterOperand(addee,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(isNegative,
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_AND,
+ new OPT_RegisterOperand(subtractee,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(isPositive,
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, result.copy(), MO_CONV(DW)));
EMIT(MIR_BinaryAcc.create(IA32_ADD, result.copy(), new OPT_RegisterOperand(
addee, VM_TypeReference.Int)));
@@ -582,7 +654,7 @@
// If MAX_VALUE < value, then result := MAX_INT
OPT_Register maxInt = regpool.getInteger();
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(maxInt,
- VM_TypeReference.Int), IC(Integer.MAX_VALUE)));
+ VM_TypeReference.Int), IC(Integer.MAX_VALUE)));
EMIT(MIR_CondMove.create(IA32_CMOV, result.copy(), new OPT_RegisterOperand(
maxInt, VM_TypeReference.Int), OPT_IA32ConditionOperand.LLT()));
@@ -596,7 +668,7 @@
// If MIN_VALUE > value, then result := MIN_INT
OPT_Register minInt = regpool.getInteger();
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(minInt,
- VM_TypeReference.Int), IC(Integer.MIN_VALUE)));
+ VM_TypeReference.Int), IC(Integer.MIN_VALUE)));
EMIT(MIR_CondMove.create(IA32_CMOV, result.copy(), new OPT_RegisterOperand(
minInt, VM_TypeReference.Int), OPT_IA32ConditionOperand.LGT()));
@@ -606,7 +678,7 @@
// If FP0 was classified as a NaN, then result := 0
OPT_Register zero = regpool.getInteger();
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(zero,
- VM_TypeReference.Int), IC(0)));
+ VM_TypeReference.Int), IC(0)));
EMIT(MIR_CondMove.create(IA32_CMOV, result.copy(), new OPT_RegisterOperand(
zero, VM_TypeReference.Int), OPT_IA32ConditionOperand.PE()));
@@ -619,9 +691,9 @@
int offset = -burs.ir.stackManager.allocateSpaceForConversion();
OPT_StackLocationOperand sl = new OPT_StackLocationOperand(true, offset, QW);
OPT_StackLocationOperand sl1 = new OPT_StackLocationOperand(true,
- offset + 4, DW);
+ offset + 4, DW);
OPT_StackLocationOperand sl2 = new OPT_StackLocationOperand(true, offset,
- DW);
+ DW);
EMIT(MIR_Move.create(IA32_FMOV, sl, Unary.getVal(s)));
OPT_RegisterOperand i1 = Unary.getResult(s);
OPT_RegisterOperand i2 = new OPT_RegisterOperand(regpool
@@ -637,16 +709,16 @@
int offset = -burs.ir.stackManager.allocateSpaceForConversion();
OPT_StackLocationOperand sl = new OPT_StackLocationOperand(true, offset, QW);
OPT_StackLocationOperand sl1 = new OPT_StackLocationOperand(true,
- offset + 4, DW);
+ offset + 4, DW);
OPT_StackLocationOperand sl2 = new OPT_StackLocationOperand(true, offset,
- DW);
+ DW);
OPT_Operand i1, i2;
OPT_Operand val = Unary.getVal(s);
if (val instanceof OPT_RegisterOperand) {
OPT_RegisterOperand rval = (OPT_RegisterOperand) val;
i1 = val;
i2 = new OPT_RegisterOperand(regpool.getSecondReg(rval.register),
- VM_TypeReference.Int);
+ VM_TypeReference.Int);
} else {
OPT_LongConstantOperand rhs = (OPT_LongConstantOperand) val;
i1 = IC(rhs.upper32());
@@ -659,7 +731,7 @@
/**
* Expansion of ROUND_TO_ZERO.
- *
+ *
* @param s the instruction to expand
*/
protected final void ROUND_TO_ZERO(OPT_Instruction s) {
@@ -673,7 +745,7 @@
// Store the FPU Control Word to a JTOC slot
OPT_MemoryOperand M = OPT_MemoryOperand.BD(regOp.copyRO(),
- VM_Entrypoints.FPUControlWordField.getOffset(), W, null, null);
+ VM_Entrypoints.FPUControlWordField.getOffset(), W, null, null);
EMIT(MIR_UnaryNoRes.create(IA32_FNSTCW, M));
// Set the bits in the status word that control round to zero.
// Note that we use a 32-bit and, even though we only care about the
@@ -685,7 +757,7 @@
/**
* Expansion of INT_DIV and INT_REM
- *
+ *
* @param s the instruction to expand
* @param result the result operand
* @param val1 the first operand
@@ -693,21 +765,28 @@
* @param isDiv true for div, false for rem
*/
protected final void INT_DIVIDES(OPT_Instruction s,
- OPT_RegisterOperand result, OPT_Operand val1, OPT_Operand val2,
- boolean isDiv) {
+ OPT_RegisterOperand result, OPT_Operand val1, OPT_Operand val2,
+ boolean isDiv) {
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), val1));
- EMIT(MIR_ConvertDW2QW.create(IA32_CDQ, new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), val1));
+ EMIT(MIR_ConvertDW2QW.create(IA32_CDQ,
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int)));
if (val2 instanceof OPT_IntConstantOperand) {
OPT_RegisterOperand temp = regpool.makeTempInt();
EMIT(MIR_Move.create(IA32_MOV, temp, val2));
val2 = temp.copyRO();
}
- EMIT(MIR_Divide.mutate(s, IA32_IDIV, new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), val2, GuardedBinary.getGuard(s)));
+ EMIT(MIR_Divide.mutate(s,
+ IA32_IDIV,
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int),
+ val2,
+ GuardedBinary.getGuard(s)));
if (isDiv) {
EMIT(MIR_Move.create(IA32_MOV, result.copyD2D(), new OPT_RegisterOperand(
getEAX(), VM_TypeReference.Int)));
@@ -719,106 +798,116 @@
/**
* Expansion of LONG_ADD_ACC
- *
+ *
* @param s the instruction to expand
* @param result the result/first operand
* @param value the second operand
*/
protected final void LONG_ADD(OPT_Instruction s, OPT_RegisterOperand result,
- OPT_Operand value) {
+ OPT_Operand value) {
OPT_Register lhsReg = result.register;
OPT_Register lowlhsReg = regpool.getSecondReg(lhsReg);
if (value instanceof OPT_RegisterOperand) {
OPT_Register rhsReg = ((OPT_RegisterOperand) value).register;
OPT_Register lowrhsReg = regpool.getSecondReg(rhsReg);
- EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowrhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.mutate(s, IA32_ADC, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(rhsReg,
- VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_ADD,
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowrhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.mutate(s,
+ IA32_ADC,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(rhsReg,
+ VM_TypeReference.Int)));
} else {
OPT_LongConstantOperand rhs = (OPT_LongConstantOperand) value;
int low = rhs.lower32();
int high = rhs.upper32();
if (low == 0) {
EMIT(MIR_BinaryAcc.mutate(s, IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), IC(high)));
+ VM_TypeReference.Int), IC(high)));
} else {
EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), IC(low)));
+ VM_TypeReference.Int), IC(low)));
EMIT(MIR_BinaryAcc.mutate(s, IA32_ADC, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), IC(high)));
+ VM_TypeReference.Int), IC(high)));
}
}
}
/**
* Expansion of LONG_SUB_ACC
- *
+ *
* @param s the instruction to expand
* @param result the result/first operand
* @param value the second operand
*/
protected final void LONG_SUB(OPT_Instruction s, OPT_RegisterOperand result,
- OPT_Operand value) {
+ OPT_Operand value) {
OPT_Register lhsReg = result.register;
OPT_Register lowlhsReg = regpool.getSecondReg(lhsReg);
if (value instanceof OPT_RegisterOperand) {
OPT_Register rhsReg = ((OPT_RegisterOperand) value).register;
OPT_Register lowrhsReg = regpool.getSecondReg(rhsReg);
- EMIT(MIR_BinaryAcc.create(IA32_SUB, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowrhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.mutate(s, IA32_SBB, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(rhsReg,
- VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_SUB,
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowrhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.mutate(s,
+ IA32_SBB,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(rhsReg,
+ VM_TypeReference.Int)));
} else {
OPT_LongConstantOperand rhs = (OPT_LongConstantOperand) value;
int low = rhs.lower32();
int high = rhs.upper32();
if (low == 0) {
EMIT(MIR_BinaryAcc.mutate(s, IA32_SUB, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), IC(high)));
+ VM_TypeReference.Int), IC(high)));
} else {
EMIT(MIR_BinaryAcc.create(IA32_SUB, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), IC(low)));
+ VM_TypeReference.Int), IC(low)));
EMIT(MIR_BinaryAcc.mutate(s, IA32_SBB, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), IC(high)));
+ VM_TypeReference.Int), IC(high)));
}
}
}
/**
* Expansion of RDTSC (called GET_TIME_BASE for consistency with PPC)
- *
+ *
* @param s the instruction to expand
* @param result the result/first operand
*/
protected final void GET_TIME_BASE(OPT_Instruction s,
- OPT_RegisterOperand result) {
+ OPT_RegisterOperand result) {
OPT_Register highReg = result.register;
OPT_Register lowReg = regpool.getSecondReg(highReg);
EMIT(MIR_RDTSC.create(IA32_RDTSC, new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lowReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(highReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int)));
}
/**
* Expansion of LONG_MUL_ACC
- *
+ *
* @param s the instruction to expand
* @param result the result/first operand
* @param value the second operand
*/
protected final void LONG_MUL(OPT_Instruction s, OPT_RegisterOperand result,
- OPT_Operand value) {
+ OPT_Operand value) {
// In general, (a,b) * (c,d) = (l(a imul d)+l(b imul c)+u(b mul d), l(b mul
// d))
OPT_Register lhsReg = result.register;
@@ -827,31 +916,40 @@
OPT_Register rhsReg = ((OPT_RegisterOperand) value).register;
OPT_Register lowrhsReg = regpool.getSecondReg(rhsReg);
OPT_Register tmp = regpool.getInteger();
- EMIT(MIR_BinaryAcc.create(IA32_IMUL2, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowrhsReg,
- VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_IMUL2,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowrhsReg,
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(tmp,
- VM_TypeReference.Int), new OPT_RegisterOperand(rhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.create(IA32_IMUL2, new OPT_RegisterOperand(tmp,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), new OPT_RegisterOperand(rhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_IMUL2,
+ new OPT_RegisterOperand(tmp,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(tmp,
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), new OPT_RegisterOperand(tmp,
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_Multiply.create(IA32_MUL, new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(lowrhsReg,
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_Multiply.create(IA32_MUL,
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowrhsReg,
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_ADD,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int)));
} else {
OPT_LongConstantOperand rhs = (OPT_LongConstantOperand) value;
int low = rhs.lower32();
@@ -882,132 +980,183 @@
if (low == 0) {
// -1, 0
// CLAIM: (x,y) * (-1,0) = (-y,0)
- EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
+ EMIT(MIR_Move.create(IA32_MOV,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
EMIT(MIR_UnaryAcc.create(IA32_NEG, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int)));
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), IC(0)));
+ VM_TypeReference.Int), IC(0)));
} else if (low == 1) {
// -1, 1
// CLAIM: (x,y) * (-1,1) = (x-y,y)
- EMIT(MIR_BinaryAcc.create(IA32_SUB, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_SUB,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
} else {
// -1, *
// CLAIM: (x,y) * (-1, z) = (l(x imul z)-y+u(y mul z)+, l(y mul z))
EMIT(MIR_BinaryAcc.create(IA32_IMUL2, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), IC(low)));
- EMIT(MIR_BinaryAcc.create(IA32_SUB, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), IC(low)));
+ EMIT(MIR_BinaryAcc.create(IA32_SUB,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), IC(low)));
- EMIT(MIR_Multiply.create(IA32_MUL, new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), IC(low)));
+ EMIT(MIR_Multiply.create(IA32_MUL,
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_Move.create(IA32_MOV,
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_ADD,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int)));
}
} else if (high == 0) {
if (low == -1) {
// 0, -1
// CLAIM: (x,y) * (0,-1) = (u(y mul -1)-x, l(y mul -1))
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), IC(-1)));
- EMIT(MIR_Multiply.create(IA32_MUL, new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.create(IA32_SUB, new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), IC(-1)));
+ EMIT(MIR_Multiply.create(IA32_MUL,
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_Move.create(IA32_MOV,
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_SUB,
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_Move.create(IA32_MOV,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int)));
} else {
// 0, *
// CLAIM: (x,y) * (0,z) = (l(x imul z)+u(y mul z), l(y mul z))
EMIT(MIR_BinaryAcc.create(IA32_IMUL2, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), IC(low)));
+ VM_TypeReference.Int), IC(low)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), IC(low)));
- EMIT(MIR_Multiply.create(IA32_MUL, new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), IC(low)));
+ EMIT(MIR_Multiply.create(IA32_MUL,
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_Move.create(IA32_MOV,
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_ADD,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int)));
}
} else if (high == 1) {
if (low == -1) {
// 1, -1
// CLAIM: (x,y) * (1,-1) = (-x+y+u(y mul -1), l(y mul -1))
EMIT(MIR_UnaryAcc.create(IA32_NEG, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_ADD,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), IC(-1)));
- EMIT(MIR_Multiply.create(IA32_MUL, new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), IC(-1)));
+ EMIT(MIR_Multiply.create(IA32_MUL,
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_Move.create(IA32_MOV,
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_ADD,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int)));
} else if (low == 0) {
// 1, 0
// CLAIM: (x,y) * (1,0) = (y,0)
- EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
+ EMIT(MIR_Move.create(IA32_MOV,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), IC(0)));
+ VM_TypeReference.Int), IC(0)));
} else if (low == 1) {
// 1, 1
// CLAIM: (x,y) * (1,1) = (x+y,y)
- EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_ADD,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
} else {
// 1, *
// CLAIM: (x,y) * (1,z) = (l(x imul z)+y+u(y mul z), l(y mul z))
EMIT(MIR_BinaryAcc.create(IA32_IMUL2, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), IC(low)));
- EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), IC(low)));
+ EMIT(MIR_BinaryAcc.create(IA32_ADD,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), IC(low)));
- EMIT(MIR_Multiply.create(IA32_MUL, new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), IC(low)));
+ EMIT(MIR_Multiply.create(IA32_MUL,
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_Move.create(IA32_MOV,
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_ADD,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int)));
}
} else {
if (low == -1) {
@@ -1015,74 +1164,100 @@
// CLAIM: (x,y) * (z,-1) = (-x+l(y imul z)+u(y mul -1), l(y mul -1))
OPT_Register tmp = regpool.getInteger();
EMIT(MIR_UnaryAcc.create(IA32_NEG, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int)));
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(tmp,
- VM_TypeReference.Int), IC(high)));
- EMIT(MIR_BinaryAcc.create(IA32_IMUL2, new OPT_RegisterOperand(tmp,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(tmp,
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), IC(high)));
+ EMIT(MIR_BinaryAcc.create(IA32_IMUL2,
+ new OPT_RegisterOperand(tmp,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_ADD,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(tmp,
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), IC(low)));
- EMIT(MIR_Multiply.create(IA32_MUL, new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
- EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEAX(),
- VM_TypeReference.Int)));
- EMIT(MIR_BinaryAcc.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(getEDX(),
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), IC(low)));
+ EMIT(MIR_Multiply.create(IA32_MUL,
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
+ EMIT(MIR_Move.create(IA32_MOV,
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEAX(),
+ VM_TypeReference.Int)));
+ EMIT(MIR_BinaryAcc.create(IA32_ADD,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(getEDX(),
+ VM_TypeReference.Int)));
} else if (low == 0) {
// *, 0
// CLAIM: (x,y) * (z,0) = (l(y imul z),0)
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), IC(high)));
- EMIT(MIR_BinaryAcc.create(IA32_IMUL2, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), IC(high)));
+ EMIT(MIR_BinaryAcc.create(IA32_IMUL2,
+ new OPT_RegisterOperand(lhsReg,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int), IC(0)));
+ VM_TypeReference.Int), IC(0)));
} else if (low == 1) {
// *, 1
// CLAIM: (x,y) * (z,1) = (l(y imul z)+x,y)
OPT_Register tmp = regpool.getInteger();
- EMIT(MIR_Move.create(IA32_MOV, new OPT_RegisterOperand(tmp,
- VM_TypeReference.Int), new OPT_RegisterOperand(lowlhsReg,
- VM_TypeReference.Int)));
+ EMIT(MIR_Move.create(IA32_MOV,
+ new OPT_RegisterOperand(tmp,
+ VM_TypeReference.Int),
+ new OPT_RegisterOperand(lowlhsReg,
+ VM_TypeReference.Int)));
EMIT(MIR_BinaryAcc.create(IA32_IMUL2, new OPT_RegisterOperand(tmp,
- VM_TypeReference.Int), IC(high)));
+ VM_TypeReference.Int), IC(high)));
EMIT(MIR_Move.create(IA32_ADD, new OPT_RegisterOperand(lhsReg,
- VM_TypeReference.Int), new OPT_RegisterOperand(tmp,
- VM_TypeReference.Int)));
+ VM_TypeReference.Int), new OPT_RegisterOperand(tmp,
+ VM_TypeReference.Int)));
} else {
// *, * (sigh, can't do anything interesting...)
OPT_Register tmp = regpool.getInteger();
EMIT(MIR_BinaryAcc.create(IA32_IMUL2, new OPT_RegisterOperand(lhsReg,
- ...
[truncated message content] |
