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From: Ben J. <bj...@us...> - 2007-12-02 04:44:46
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Module Name: pcb Committed By: bjj Date: Sun Dec 2 04:44:51 UTC 2007 Modified Files: pcb/src: macro.h move.c Log Message: Fix [ 1820398 ] Inconsistant vias with move-to-layer Add explicit check for silk layer when making vias due to movelinetolayer To generate a diff of this commit: cvs rdiff -r1.27 -r1.28 pcb/src/macro.h cvs rdiff -r1.41 -r1.42 pcb/src/move.c To view the diffs online visit: http://pcb.cvs.sourceforge.net/pcb/pcb/src/macro.h?r1=1.27&r2=1.28 http://pcb.cvs.sourceforge.net/pcb/pcb/src/move.c?r1=1.41&r2=1.42 Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. |